JPS648423A - Key scanning system for key input device - Google Patents

Abstract

PURPOSE:To suppress the increment of the number of I/O ports even if the number of key switches is increased and to detect key depression within a short period by allowing a scanning pulse generating circuit to scan the X address line of a key matrix and allowing a CPU to apply only a start pulse. CONSTITUTION:When the CPU 11 outputs a start pulse, the phase of a frequency divider 14 is initialized, a quaternary counter 15 is cleared and output lines QA, QB are initialized. Every input of a clock pulse CP, the counter 15 counts up its contents and the output lines QA, QB output four states, (QA, QB)=(0, 0), (1, 0), (0, 1), (1, 1). The four states are decoded by a decoder 16, and during the period that a pulse L is generated in X address lines X1, X4 the CPU 11 reads in the states of all Y address lines Y1-Y4, and executes a series of processing. After generating the start pulse, the series of operation is repeated 4 times to enter information relating to the depressing states of all the key switches.