JPS5561806A - Sequence controller - Google Patents

Sequence controller

Info

Publication number
JPS5561806A
JPS5561806A JP13418978A JP13418978A JPS5561806A JP S5561806 A JPS5561806 A JP S5561806A JP 13418978 A JP13418978 A JP 13418978A JP 13418978 A JP13418978 A JP 13418978A JP S5561806 A JPS5561806 A JP S5561806A
Authority
JP
Japan
Prior art keywords
memory
keyboard
program
designated
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13418978A
Other languages
Japanese (ja)
Other versions
JPS603209B2 (en
Inventor
Keisuke Kawashima
Hideaki Nakamura
Yoshitane Saito
Kenji Nishikido
Kiyoto Hirase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP13418978A priority Critical patent/JPS603209B2/en
Publication of JPS5561806A publication Critical patent/JPS5561806A/en
Publication of JPS603209B2 publication Critical patent/JPS603209B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Control By Computers (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE: To enable program input with key input from the keyboard without using a pin board.
CONSTITUTION: The central processing unit CPU is controlled with the program in the fixed memory ROM and inputs the operation sequence program from the keyboard 1 to the memory M sequentially with the instruction of the console switches CS and S2. The operator operates the keyboard 1, while monitoring various display unit groups 2W4' and 51W54. During the sequence execution, CPU sequentially reads out the sequence program from the memory M while scanning and monitoring the input terminals IN1WINn at all times, performs logical operation designated by the signal at the input terminal designated with the instruction and outputs the results to the output terminals OUT1WOUTn designated. The content of the memory M unnecessary is erased with simultaneous operation of a plurality of keys.
COPYRIGHT: (C)1980,JPO&Japio
JP13418978A 1978-10-30 1978-10-30 sequence controller Expired JPS603209B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13418978A JPS603209B2 (en) 1978-10-30 1978-10-30 sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13418978A JPS603209B2 (en) 1978-10-30 1978-10-30 sequence controller

Publications (2)

Publication Number Publication Date
JPS5561806A true JPS5561806A (en) 1980-05-09
JPS603209B2 JPS603209B2 (en) 1985-01-26

Family

ID=15122506

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13418978A Expired JPS603209B2 (en) 1978-10-30 1978-10-30 sequence controller

Country Status (1)

Country Link
JP (1) JPS603209B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0482304U (en) * 1990-11-27 1992-07-17

Also Published As

Publication number Publication date
JPS603209B2 (en) 1985-01-26

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