JPS648377B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a floating point arithmetic unit that is additionally attached to an electronic computer.

There are two ways to perform floating point operations on an electronic computer. One is completely software-based, the other is dedicated hardware,
That is, this is a method of adding a floating point arithmetic unit and using that unit. The present invention relates to the latter.

In order to increase the speed of conventional floating point arithmetic devices, an independent device was fabricated for each floating point arithmetic operation. In addition, in order to reduce costs, in order to use modules such as bit shifters and arithmetic logic units in common for each floating-point operation, registers are installed in the floating-point operation circuit, and floating-point operations are controlled by firmware. Decimal point operations were performed by analyzing them into partial processes in the firmware execution cycle. The former requires a large-scale circuit and is expensive. The latter method uses firmware, so it has the disadvantage of requiring a long processing time.

The purpose of the present invention is to reduce the size and cost of the circuit by common use of modules, and to increase the speed by static control from the main processor unit, in order to eliminate these conventional drawbacks. It is an object.

The floating point arithmetic device of the present invention includes two input registers for storing an arithmetic number and an operand, an arithmetic circuit for performing floating point arithmetic, and an arithmetic operation circuit that uses the output of the input register and the output of the arithmetic circuit as input signals. A first selector selects an input signal using two control signals from the main processor unit and outputs the selected input signal to the arithmetic circuit.
a second selector circuit which receives the output of the arithmetic circuit as an input signal and selects and outputs the input signal according to a control signal from the main processor unit; It consists of an output register that stores the calculation results. The configuration of the present invention is shown in FIG.
In the figure, 200 and 201 are input registers, 202 is a selector circuit, 203 is an arithmetic circuit consisting of a plurality of arithmetic modules, 204 is a selector circuit, and 205 is an output register. Connections and signal flows are shown by solid lines with arrows.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to drawings showing embodiments. The types of floating point operations in this embodiment include fixed point-floating point conversion,
These are floating point to fixed point conversion, floating point output of floating point numbers, floating point addition, floating point subtraction, floating point multiplication, and floating point division. Furthermore, floating point data consists of 8 bits for the exponent and 12 bits for the mantissa, while fixed point data consists of 16 bits.

FIG. 2 is a block diagram showing the overall configuration of an embodiment of the present invention. 301 and 302 are each 20
It shows a bit input register and 324 is a 20-bit output register. Numerals 303 to 307 are multiplexers that select inputs to subsequent modules according to processing operations, and a set of these multiplexers constitutes the selector circuit 202. 3
Numerals 20 to 323 are multiplexers that select outputs based on processing calculations, and these multiplexers constitute the selector circuit 204. 320
The multiplexer 321 selects the mantissa sign bit of the output, the multiplexer 321 selects the mantissa sign bit of the output, and the multiplexer 322
323 selects the sign bit of the exponent part of the output, and 323 selects the exponent part of the output. The flow of processing is determined by these multiplexers. 308 is a field programmable logic array (hereinafter referred to as
(abbreviated as FPLA).

FPLA is an LSI consisting of a collection of gates, and the user can create any connections between the gates to realize any combinational logic circuit. FPLA has a limit on the number of input bits and output bits, so 1
If the number of input/output bits exceeds the number of input/output bits of a single FPLA, signals with a large number of input/output bits can be handled by arranging multiple FPLAs in parallel. 309 is an FPLA that realizes left shift of arbitrary bits up to 16 bits. 310 is an FPLA that realizes an arbitrary bit right shift of up to 12 bits. 311 is an FPLA that realizes arbitrary bit left shift up to 12 bits and 1 bit right shift. 312 and 313 are 4-bit Aristate logic arrays (hereinafter abbreviated as ALU);
314 is 8-bit ALU, 315 is 12-bit ALU.
It is an ALU. Reference numeral 316 is a combinational logic circuit composed of gates, which is used to create an exponent part mask and a left bit shift FPLA control input signal when a floating point number is displayed as a floating point number. 317 is a 12-bit multiplier, and 318 is a 12-bit multiplier.
It is a bit divider. Reference numeral 319 denotes a selection circuit which selects the mantissa part by comparing the exponent part in the case of floating point addition/subtraction and calculates the number of shift bits of the mantissa part. The arithmetic circuit 203 is composed of the various arithmetic modules 308 to 319 described above. Next, the operation will be explained using floating point addition and subtraction as an example.

The signal lines indicated by real numbers and dotted lines in the figure are signal lines indicating connections between each module in the embodiment,
The signal lines indicated by dotted lines are distinguished in order to explain the operation using floating point addition and subtraction as an example. When a floating-point addition/subtraction execution instruction comes from the main processor, the steps from 303 to 307,320
323 multiplexers are controlled, and a processing path is generated according to the dotted signal line. The output signal line 305 of the input register 301 and the output signal line 351 of the input register 302 are input to the selector circuit 319. The signal on signal line 350 represents the exponent part of one operand in floating point format, and the signal on signal line 351 represents the exponent part of another operand in floating point format, both of which are connected to selection circuit 319.
The larger one is selected and output to the signal line 352. In addition, the input signal of the signal line 350 and the signal line 35
For the mantissa part of the input signal 1, the one with the larger exponent part is selected and the one with the smaller exponent part is selected, and the selection circuit 3 is connected to the signal line 354.
It is output from 19. The mantissa signal on the signal line 354 with the smaller exponent part is selected by the multiplexer 305, output to the signal line 357, and input to the FPLA 309. At this time, the difference signal between the exponent parts of the two numbers is also
Input to FPLA310. In FPLA310,
This input mantissa signal is bit-shifted to the right by the difference in the exponent part. This operation adjusts the bit positions for mantissa addition and subtraction.
The output signal of the FPLA 310 is output to a signal line 364, and the 12-bit ALU 315 performs addition and subtraction with the mantissa signal of the signal line 353 with the larger exponent part, and the resultant signal is output to a signal line 355. The signal on the signal line 355 is selected by the multiplexer 303, output to the signal line 356, and input to the FPLA 308. FPLA30
8, the number of shift bits required for normalization is calculated and output to the signal line 365. signal line 36
The output signal 5 is input as a control signal to the FPLA 311, and the FPLA 311 shifts the output 355 of the addition/subtraction of the mantissa part of the 12-bit ALU 315. At this time, the right shift is performed by a maximum of 1 bit, and the left shift is performed by a maximum of 12 bits. FPLA31
The output of 1 is outputted to the signal line 359, selected by the multiplexer 321 and the multiplexer 320, and outputted to the signal lines 361 and 360, and becomes the mantissa input and the sign input of the mantissa of the output register 324, respectively. Further, the shift bit number signal for normalizing the addition/subtraction result of the mantissa part of the signal line 365 calculated by the FPLA 308 and the larger exponent part data of the signal of the signal line 352 selected by the selection circuit 319 are sent to the 8-bit ALU 314. The addition is performed and output on signal line 358. The output signal of the signal line 358 is sent to the multiplexer 323 and the multiplexer 32.
2 input signal, selected signal line 363, 3
62, and serve as the exponent part input and exponent part sign input of the output register 324, respectively. Although the processing of this embodiment has been explained above using floating point addition and subtraction as an example, other floating point operations can be similarly performed by controlling the multiplexer with control signals from the main processor unit. , the processing paths corresponding to each floating-point operation are connected,
After a period of time specific to each floating point operation has elapsed, the result of the operation is available in the output register.

FIG. 3 shows a detailed circuit diagram of the combinational logic circuit 316 of FIG. 2, which consists of two independent circuits 3A and 3B. 3A in FIG. 3 is a mask for the exponent part. The exponent sign bit of signal line 401 is ANDed with the exponent parts of signal lines 402 to 408 to obtain outputs of signal lines 409 to 415. For example, if the exponent part sign bit is 0, that is, positive, the exponent part is forcibly set to 0, and if the exponent part sign bit is 1, that is, negative, the exponent part is passed through as is. This process yields the exponent part of the floating point representation of the number below the decimal point.

3B in FIG. 3 is a circuit for obtaining the shift bit number of the mantissa part to obtain the mantissa part of the above-mentioned floating point representation. This is because the mantissa needs to be shifted to represent the decimal places when expressed in decimal notation. The signal line 450 is the sign bit of the exponent part, the signal lines 451 to 453 are the upper 3 bits of the exponent part, and the signal lines 454 to 457 are the lower 4 bits of the exponent part, 458 to 461.
The signal line is an output corresponding to the number of shift bits. If the exponent is negative, all outputs are 1 and no shift is performed, and if the exponent is 16 or more, the output is 0 and the mantissa is filled with 0.

FIG. 4 shows a specific example of the selection circuit 319 in FIG. 2. This circuit uses 2 when performing floating point addition/subtraction.
A shift is performed by comparing the exponent parts of two numbers, the mantissa part is selected to match the bit position, and the number of shift bits is generated. A comparator 553 compares the exponent inputs of the signal lines 508 and 509, and if the signal on the signal line 508 is large, it outputs 1 to the signal line 510, and if the signal on the signal line 509 is large, it outputs 0 to 510. Output. The signal on signal line 510 is 550,5
This becomes the selection signal for the 51 and 552 multiplexers, and the signal line 50 is used for the 550 multiplexers.
1,502 is selected and outputted to the signal line 505, and for the multiplexer 551, the smaller mantissa input of the signal lines 503 and 504 is selected and outputted to the signal line 506. For the multiplexer, signal lines 503, 5
Select the larger mantissa input of 04 and connect the signal line 50.
Output to 7. Also, the output signal of the signal line 510 is 5
This is a control signal for the mantissa shift bit number calculation circuit of 54. 554 is a mantissa shift bit number calculation circuit for aligning the digits of the mantissa in floating point addition and subtraction, and the absolute value of the difference between the exponent inputs of signal lines 508 and 509 is output to signal line 511.

According to the present invention, by using a bit shifter and ALU in common for each floating point operation as shown in Fig. 2, the number of these used is small (in this embodiment, it was configured with about 100 ICs), and the cost is reduced. is small. Also, each floating point calculation process is
Since control is performed only by static control signals from the main processor unit, there is no wasted time unlike when firmware is used, and high-speed execution is possible. Schottky's
When using an IC, floating point addition can be executed in 250 nsec, and floating point multiplication can be executed in about 250 nsec.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the configuration of the present invention, Figure 2 is a block diagram showing the configuration of the present invention.
3 is a detailed diagram of the combinational logic circuit in the embodiment of FIG. 2, and FIG. 4 is a detailed diagram of the selection circuit in the embodiment of FIG. 2. It is. In the figure, 200, 201...input register,
202, 204...Selector circuit, 203...Plural calculation modules, 205...Output register, 301, 302, 324...Register, 30
3,304,305,306,307,320,
321, 322, 323...Multiplexer, 3
08,309,310,311...FPLA, 31
2,313,314,315...ALU, 316
... Combinational logic circuit, 317 ... Multiplier, 3
18... Division circuit, 319... Selector circuit, 5
50,551,552...Multiplexer, 55
3... Comparator, 554... Absolute value calculation circuit for difference.

Claims (1)

[Claims] 1 After the operation, an arithmetic circuit consisting of two input registers for storing the operands and a plurality of arithmetic modules for performing floating point calculations, and the output of the input register and the plurality of outputs of the arithmetic circuit are input. a first selector circuit comprising a plurality of multiplexers which selects the input signal according to a control signal from a main processor unit and outputs the input signal to each arithmetic module of the arithmetic circuit; a second selector circuit consisting of a plurality of multiplexers which take the input signal as an input signal and select and output the input signal according to a control signal from the main processor unit; A floating point arithmetic unit comprising: an output register;