JPH06139217A - Highly precise processing unit and method - Google Patents

Abstract

PURPOSE:To perform a highly precise arithmetic processing by a neuro com puter, which performs fixed-point and single-precision arithmetic processing without increasing a circuit scale and lowering the arithmetic processing speed. CONSTITUTION:The neuro computer 10 consists of plural neuro boards 12 which perform neural network operation and a control board 11. Further, the control board 11 consists of a neural network controller 13 which controls the neuro computer 10, a control storage 15 which stores microprograms, and a global memory 16 which stores the values of input layer neurons, etc. Then the neural network controller 13 decodes and executes the microprogram codes stored in the control storage 15 to performs the arithmetic processing of neural network operation having higher precision than single precision.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to arithmetic processing in a neuron in a neurocomputer that performs neural network operation by fixed point and single precision arithmetic processing, and more specifically, each arithmetic unit used in the single precision arithmetic processing is The present invention relates to an information processing device and a high-precision arithmetic processing method that enable higher-precision arithmetic processing using the same.

[0002]

2. Description of the Related Art Currently, software simulation using an existing Neumann computer is the mainstream for the execution of neural networks. In general, such software simulation can improve the accuracy of the input / output values of the neuron relatively easily by changing the program description. However, there are many restrictions on the processing speed of neural network operation,
It was expected that a neuro computer that could realize neural network operation with hardware would emerge. Therefore, the practical application of a neuro computer that can learn at high speed with a large-scale neural network is being studied. For example, in 1990, IEICE Transactions (NC90-1
In the neurocomputer announced in 2) under the heading "High-speed learning type neuro-WSI", the back propagation learning method is speeded up by connecting digital neurons with a bus type network and communicating between the digital neurons in a time division manner. I can do it.

[0003]

However, in order to further improve the calculation accuracy, the neurocomputer realized by hardware has, for example, a bit width of the multiplier input value corresponding to the problem to be multiplied. Cannot be made variable. Therefore, it is possible to expand the bit width of the input / output value of the multiplier of the neurocomputer in advance, but in general, it is necessary to increase the bit width of the multiplier input for high-precision arithmetic that is considered to be rarely used. If a dedicated arithmetic circuit is provided for increasing the number of pixels and performing high-precision arithmetic, the efficiency of use of the arithmetic circuit with respect to the chip area will decrease. Even if the high-precision arithmetic processing itself can be sped up compared to software simulation by adding a dedicated arithmetic circuit for performing high-precision arithmetic processing, the chip area is expanded by expanding the circuit scale,
An increase in chip cost can be considered. The present invention provides a high-precision arithmetic processing method capable of performing high-speed and high-accuracy arithmetic processing without expanding the circuit scale in this way, and an information processing apparatus capable of realizing the arithmetic processing method. This is a problem to be solved.

[0004]

As a first means, the output value of each arithmetic unit, such as a multiplier and an adder, and a high-precision arithmetic operation to be described later are performed so that an arithmetic operation with higher precision than single precision arithmetic processing can be performed. A CCR capable of detecting a carry, an overflow, a sign, and a value of 0 of the value of the processed multiplier word and multiplicand word is provided in the neuron. Further, in order to perform high-precision multiplication described later, a storage device capable of storing the output value of each arithmetic unit, the multiplier word, and the multiplicand word is provided in the neuron, and the value stored here is calculated by the arithmetic unit again. Provide a bus that can be processed. further,
In order to reduce coding mistakes in microprograms, the number of machine cycles required for pipeline processing is made equal when broadcasting neuron state values from the input layer to the intermediate layer and when broadcasting from the intermediate layer to the output layer. Provide a latch. The neural network is controlled by using a microprogram so that the form of the neural network and the calculation accuracy can be freely selected.

As a second means, as a high precision multiplication method for performing arithmetic processing with higher precision than single precision arithmetic, even for multipliers and multiplicands exceeding the input bit width of the multiplier, single precision provided in the neuron in advance. The multiplier and the multiplicand are divided into a plurality of words within a range not exceeding the input bit width of the single precision multiplier so that the multiplier can be multiplied, and the divided multiplier word and the divided word are multiplied, and the product is obtained. A high precision multiplication method for calculation is used. Further, when the two's complement representation is used for the multiplier and the multiplicand which are the input values of the multiplier, it is necessary to preprocess the above-mentioned divided multiplier word and multiplicand word. .

1. The most significant bit of the lower word is added to the least significant bit of the upper word of the divided multiplier word and multiplicand word. CCR is used to detect the state of the most significant bit of the lower word. 2. Zeros are filled from the most significant bit side of words other than the most significant word of the divided multiplier word and multiplicand word.
If the value is negative, sign extension is performed on the most significant word.

A plurality of words which have been subjected to these preprocessing methods are stored in a storage device and again multiplied by a multiplier, and partial products are added together and digits are added together to obtain a product with higher precision than single precision multiplication. You can The product is represented by a plurality of words obtained by adding partial products. Further, since the arithmetic processing is performed for each divided word as in the single precision arithmetic processing, it is possible to perform the highly accurate arithmetic processing even in the shift processing and the ALU processing.

[0008]

By using the first means, the carry value, the overflow, the sign, and the value of the output value of each arithmetic unit such as a multiplier and an adder, the multiplier word processed for high-precision arithmetic, and the value of the multiplicand word are By being able to detect each state of 0 or not, and temporarily storing the output value of each arithmetic unit, the multiplier word, and the multiplicand word, the stored value can be processed again by the arithmetic unit. The high-precision arithmetic processing method described in the means of 2 has become possible. Further, since the high precision multiplication processing decodes and executes the microprogram in the same manner as single precision, both single precision and high precision arithmetic processing can be performed by the same neuron architecture. Moreover, since a new circuit dedicated to high-precision arithmetic processing is not added, the circuit scale is not expanded and the chip area is not expanded as compared with the circuit for single-precision arithmetic processing.

By using the second means, the input / output data of each arithmetic unit can be divided into a plurality of words, so that the bit width can be made larger than the input / output data of each arithmetic unit for single precision operation. In the high-precision multiplication processing based on the output data, the high-precision multiplication processing can be performed by performing the preprocessing described in the second means, and a product with higher precision than single precision can be obtained.
Further, in the shift process and the ALU process, the input / output data has a bit width larger than that of the input / output data used for the single precision calculation. Since the calculation is performed based on a plurality of divided data, the precision is higher than the single precision calculation process. You can perform various calculations.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a device capable of performing a higher precision operation in a neurocomputer that performs fixed-point and single-precision operations and a high-precision multiplication method using this device will be described below, and finally, these will be used. The operation of the high precision multiplication process will be described in detail.

As an example of the neuro computer using the present invention, the outline of the neuro computer will be described first.

FIG. 1 is a block diagram of a neurocomputer using the present invention. The neuro computer 10 is composed of a plurality of neuro boards 12 that perform neural network operations and a control board 11. Also, the control board 11 is
It is composed of a neural network control device 13, a control storage 15, and a global memory 16.
The neural network control device 13 controls the neuro computer 10 by decoding and executing the micro program code stored in the control storage 15. The neural network control device 13
Is a control storage control circuit 14a for decoding and executing the micro program code stored in the control storage 15, and an external bus is provided as a communication means between the workstation 18 and the neuro computer 10 to control the external bus. ,
It is composed of a neuron control circuit 14c for controlling neurons in the neurochip 17 and a global memory control circuit 14d for storing values of input layer neurons and the like. still,
The external bus is connected to a memory, a CPU and a SCSI board, and the SCSI board is a workstation 18 having a micro generator for generating micro program code.
Connected to. Since the present invention relates to pipeline processing between the control board 11 and the neuro board 12 and high-precision calculation in the neuro chip 17, the neural network pipeline processing and the neuro chip 17 will be described below.

In the present invention, in order to prevent the occurrence of coding mistakes in the microprogram code controlling the neurocomputer 10, the state values of neurons are broadcast from the input layer to the intermediate layer and from the intermediate layer to the output layer. Set the required number of machine cycles to the same. With this setting, when the neuron 20 fetches an input value when performing a high-precision arithmetic operation, NOP (NO OPERATION) of 9 machine cycles occurs, so that the multiplicand preprocessing of the high-precision multiplication processing described later is performed during this period. The pipeline configuration will be described below.

FIG. 2 shows the pipeline structure and the internal structure of the neurochip 17 shown in FIG. still,
The neurochip 17 of FIG. 2 is composed of a plurality of neurons 20 corresponding to the brain cells of a living being.

First, the pipeline structure of the neural network operation will be described. A pipeline shown by a broken line in FIG. 2 is a pipeline for control signals, and a pipeline shown by a solid line is a pipeline for data.
The numbers attached to each pipeline are the control storage 1 by the control storage control circuit 14a.
5 is a time series of machine cycles until the microprogram stored in 5 is decoded and executed.

First, the number of machine cycles when the neuron 20 broadcasts a value to another different neuron 20 will be described. In FIG. 2, it takes 7 machine cycles until the control storage control circuit 14a decodes the value output instruction for the neuron 20 and the control signal reaches the neuron 20. Next, this neuron 20 outputs a value, and this value passes through the control board 11 and the neural network control device 13 to the neuro board 12 in which another neuron 20 exists,
A total of 16 machine cycles are required before inputting to another neuron 20 via the neurochip 17.

Secondly, the value of the input layer neuron is stored in the global memory 16, and the number of machine cycles until this value is stored in the neuron 20 will be described.
In FIG. 2, the control storage control circuit 14a
Takes 5 machine cycles until the control signal reaches the global memory 16 after decoding the value output instruction to the global memory 16. Next, in order to make the number of machine cycles described in the first and the second number of machine cycles equal to each other for the above-mentioned reason, a redundant pipeline is provided in the neural network control device 13, so that the global memory 16 is Outputs the value, neuron 2
Set the pipeline so that a total of 16 machine cycles are required before it is input to 0.

With the above pipeline configuration, the number of machine cycles required for broadcasting the state value of the neuron from the input layer to the intermediate layer and for broadcasting it from the intermediate layer to the output layer can be set equal.
Also, by adopting this pipeline configuration, for example, in the neuron 20, the global memory 16 and the neuron 20
In the case of multiplying the value in the multiplier as a multiplier, the neuron 20 decodes the microcode in the control storage 16 and takes 7 machine cycles until the control signal reaches the neuron 20, similarly from the global memory 16 or the neuron 20 to another neuron 20. It takes 16 machine cycles to reach the value of
A subtract 9 machine cycle NOP condition occurs after the multiplier in 0 fetches before the multiply instruction is executed.
During this NOP state, pre-processing for high-precision multiplication described later is performed.

Next, the detailed internal structure of the neuron 20 having means for performing high-precision multiplication, which will be described later, will be described.

FIG. 3 shows a block diagram of the neuron 20 in FIG. The structure will be described. Input / output of data to / from the neuron 20 is performed via the input / output bus. or,
The command for the neuron 20 is input to the neuron 20 via the command bus and transmitted to each logic circuit via the control circuit. A register file 3 is used as a storage device for each data.
0, RAM 31a, RAM 31b, and the register file 30 can store all data output to the F bus. Therefore, it is possible to store a word or the like processed for high-precision arithmetic described later, and input the value again to the arithmetic unit to process it, thereby enabling high-precision multiplication described later. Further, the flip-flop (FF) group for performing the multi-stage pipeline processing is
FF32a, FF32b, FF32c, FF32d, F
It is composed of five F32e, and the bus in the neuron 20 is composed of seven buses A, B, C, D, E, F, and G. The present invention enables the high-precision multiplication described later by providing the E bus. By providing this E bus, the multiplication result product of the multiplier 33 can be calculated by the ALU3 in the single precision operation.
The shift processing can be performed directly by the shifter 36 without passing through the 4 and the FF 32d. In addition, by providing the same E bus for high precision arithmetic,
Even if the LU 34 is in the process of calculation, the product of the multiplication result of the multiplier 33 is passed through the shifter 36, and the register file 30
Can be stored in the ALU 34 and the stored value can be calculated again in the ALU 34 and the multiplier 33, which enables high-precision calculation to be described later. Further, in the present invention, the CCR 35 is divided into a plurality of words for high-precision calculation, in addition to detecting the state of each value in single-precision calculation, a value having a bit width larger than single-precision is divided,
By using this divided word as well, high-precision arithmetic processing described later can be performed.

Next, the preprocessing and high-precision calculation of the high-precision multiplication using the above-mentioned neuron circuit will be described below.
In high-precision multiplication, not only multiplication but also addition, shift, and the like are calculated as described below, and therefore high-precision multiplication will be described as an example with reference to FIG. FIG. 4 shows a method of multiplying the multiplicand upper word 40a and the multiplicand lower word 40b divided into two words by the multiplier upper word 41a and the multiplier lower word 41b similarly divided into two words. The products obtained by multiplying each word correspond to the partial product 42, the partial product 43, the partial product 44, and the partial product 45.

First, it is assumed that the input data bit width of the multiplier in the target arithmetic processing device exceeds the bit width of the multiplier in all of the multiplicand, the multiplier and the product. Under this assumption, multiplication by the conventional method cannot be performed, so a multiplier,
Both the multiplicand are divided into some words (in FIG. 4, all are divided into two words). First, multiplicand lower word 4
The following high-precision multiplication preprocessing is performed on the high-order word 40a of the multiplicand so that normal multiplication can be performed even if the arithmetic unit in the neuron chip treats the most significant bit of 0b as a sign bit. The most significant bit of the multiplicand lower word 40b is added to the least significant bit of the higher word 40a of the multiplicand. Next, in the example of FIG. 4, the previously divided words are multiplied four times, and the respective digits are aligned and added. Specifically, there are the following four ways.

1. Multiplicand lower word 40b × multiplier lower word 41b = partial product 42 2. Multiplicand lower word 40b × multiplier upper word 41a =
Partial product 43 3. Multiplicand upper word 40a × multiplier lower word 41b =
Partial product 44 4. Multiplicand upper word 40a × multiplier upper word 41a =
Partial product 45 The results of adding and adding the digits of the above four partial products are as follows.

Partial product 48b = Partial product 42 + Partial product 43 Partial product 48a = Partial product 44 + Partial product 45 (+ Multiplier upper word 47 + Multiplier lower word 46) The operation in parentheses for the partial product 48a is This is performed only when a sum overflow occurs when the most significant bit of the multiplicand lower word 40b is added to the least significant bit of the upper word 40a.

As for the multiplier, the most significant bit of the lower word can be added to the least significant bit of the upper word in the same manner as the multiplicand, and more accurate multiplication is possible, but this embodiment is performed for the reason described below. Absent. Effective bits of the multiplier upper word 41a and the multiplier lower word 41b in FIG. 4 (effective bits: adjusting the bit width of the multiplier lower word 41b and the multiplier upper word 41a so that the partial product 48b and the partial product 48a do not overflow during addition). You can
In adjusting, for example, even if the bit width of the multiplier lower word 41b is 10 bits at the maximum, it is set to 8 bits so that the upper 2 bits are filled with 0 in order not to overflow. In this case, 8 bits other than 0 are defined as valid bits. ) Is appropriately adjusted to prevent overflow when adding partial products, and it is not necessary to align and add the overflowed bit caused by the overflow to the bit of the corresponding another word. Minute calculation time can be shortened. As a result of this addition, the bits of the overlapping parts of the respective words are put together as a product lower word 49b like the partial product 48b and the partial product 48a shown in FIG. It is the multiplication result (product). By using this multiplication method, the bit width of the multiplier, the multiplicand, and the product can be expanded, and highly accurate multiplication can be performed.

Next, the multiplication shown in FIG. 4 will be described in time series.

FIG. 5 is a schematic flow of high precision multiplication. The letters in the figure correspond to those in FIG. First, before the multiplier reaches the neuron 20 described with reference to FIG. 2, the multiplicand preprocessing shown in the flow 50 and the flow 51 of FIG. 5 is performed. Next, in a flow 52, the partial product 42 shown in FIG. 4 is calculated, and the multiplicand lower word 41b is stored in the register file 30 as the multiplicand lower word 46. Partial product 44 in flow 53
Calculate. The partial product 43 is calculated in the flow 54. Further, the multiplier upper word 41a is stored in the register file 30 as the multiplier upper word 47. Furthermore, the partial product 43 is set to the lower word 4 of the multiplier.
The effective bit of 1b is shifted to the left and the partial product 42 is added to this, and the sum is made a partial product 48b. In the flow 55, the partial product 45 is calculated, the partial product 45 is left-shifted by the effective bit of the multiplicand lower word 41b, and the partial product 44 is added to this,
The sum is the partial product 48a. Next, in step 56, the presence or absence of the overflow detection process performed in step 51 is judged. If there is the overflow process, the partial product 4 in flow 57 is obtained.
8a is added with the multiplicand lower word 46 and the multiplicand upper word 47 left-shifted by the effective bits of the multiplier lower word 41b, and this sum is again used as a partial product 48a. If there is no overflow processing in the flow 56, the processing in the flow 58 is performed. In the flow 58, the bit overlapped part of the partial product 48b and the partial product 48a is added to form the product lower word 49b. The overflow of this addition is added to the corresponding bit of the partial product 48a, and the sum is added to the product upper word. 49a.

Next, using the neuron architecture of FIG. 2 and the high-precision multiplication processing method of FIG. 4, the high-precision multiplication processing by pipeline operation is divided into operations for each machine cycle.
It will be described in detail corresponding to the flow of.

In the following, the individually written sentences correspond to the micro program code, and the number at the beginning of the sentence represents the number of machine cycles from the time when the high precision multiplication process is started. The flow of data and the like will be described with reference to FIG.

The machine cycles 0 to 8 correspond to the flow 50 to the flow 51 of FIG. 0. Multiplier lower word broadcast. 1. NOP (NO OPERATION: Neuron 1
No state is given to 5) 2. From the RAMs 31a and 31b, the multiplicand lower word (16
(Bit) and stored in FF32c. FF32d reset. 3. Add FF32d and FF32c in ALU34. Record the Japanese condition on CCR35. The CCR 35 can record data carry, overflow, sign, and four current states, that is, 0 or not. Incidentally, the flags of the CCR 35 are as follows, when a carry is raised 1, overflows, 1, the sign is minus 1, the value is 0, and the others are 0. 4. The ALU 34 adds the FF 32d, 0 and the code of the CCR 35. The sum is stored in FF32d. 5. The value of FF32d is 8-bit logical shift to the left. The shift result is stored in FF32d. The shift bits of the shifter 36 are 0, 1, 2, 4, 8, -1, -2, -4, -8, -16.
10 ways. 6. The value of FF32d is 8-bit logical shift to the left. The shift result is stored in the address 13 of the register file 30 (hereinafter, the address 13 of the register file 30 is an address in [] represented as RF30 [13]). Multiplier lower word broadcast. 7. Store the value of RF30 [13] in FF32b, RAM
The multiplicand upper word from 31a and 31b is stored in the FF 32c. 8. Add FF32b and FF32c and record the sum condition in CCR35. Store this sum in RF30 [13]. The machine cycle 9 to 14 is the flow 52 of FIG.
Corresponding to. 9. Store the lower word of the multiplier in FF32b and the lower word of the multiplicand in FF32c. FF32d reset. Multiplier high word broadcast. 10. Although it is NOP on the microprogram, multiplication processing is performed, and the product is stored in the FF 32e. 11. Add FF32d and FF32e. RF sum 30
Stored in [11]. 12. 16-bit arithmetic shift of FF32b (lower word of multiplier) to the right. Stored in the shift result FF 32d. 13. 4-bit logical shift of FF32d to the right. Stored in the shift result FF 32d. 14. 2-bit logical shift of FF32d to the right. Stored in shift result RF30 [12]. The machine cycles 15 to 17 correspond to the flow 53 of FIG. 15. Store the lower word of the multiplier in FF32b. RF30 [13] (multiplicand upper word) is stored in FF32c. FF32
d reset. Multiplier high word broadcast. 16. Although it is NOP on the microprogram, multiplication processing is performed, and the product is stored in the FF 32e. 17. FF32d (value is 0) and FF32 in ALU34
Add e (product). Store the sum in RF30 [10]. The machine cycles 18 to 23 correspond to the flow 54 of FIG. 18. Store the multiplier upper word in the FF 32b. Store multiplicand lower word in FF32c. 19. Although it is NOP on the microprogram, multiplication processing is performed, and the product is stored in the FF 32e. 20. 16-bit arithmetic shift of FF32b (higher word of multiplier) to the right. Stored in the shift result FF 32d. 21. 2-bit logical shift of FF32d to the right. Stored in shift result RF30 [9].

22. FF32e (product) is logically shifted to the right by 2 bits (the product from the E bus is right-justified, so it is effectively shifted by 8 bits). Stored in the shift result FF 32d. RF30 [11] is stored in FF32c. 23. Add FF32d and FF32c in ALU34.
The sum is stored in RF30 [11]. The machine cycles 24 to 27 correspond to the flow 55 of FIG. 24. Store the multiplier upper word in the FF 32b. RF30 [13] (multiplicand upper word) is stored in FF32c. 25. Although it is NOP on the microprogram, multiplication processing is performed, and the product is stored in the FF 32e. 26. FF32e (product) is right shifted by 2 bits (E
Since the product from the bus is on top, it is effectively shifted by 8 bits). Stored in the shift result FF 32d. FF32
Store RF30 [10] in c. 27. Add FF32d and FF32c in ALU34.
The sum is stored in RF30 [10]. The machine cycles 28 to 30 correspond to the flow 56 to the flow 57 of FIG. 28. If the overflow flag of the CCR 35 is set, RF30 [10] is stored in the FF 32b. FF32c
Store RF30 [12] in. 29. If the overflow flag of the CCR 35 is set, the FF 32b and the FF 32c are added by the ALU 34. Store the sum in FF32d. RF30 [9] is stored in FF32c. 30. If the overflow flag of the CCR 35 is set, the FF 32d and the FF 32c are added by the ALU 34. Store the sum in RF30 [10]. Machine cycle 31 to 4
Up to 4 corresponds to the flow 58 in FIG. 31. RF30 [11] is stored in FF32b. 32. Add 0 to FF32b in ALU34. Store the condition of the sum in CCR35. 33. If the sign flag of the CCR 35 is negative, F
Store RF30 [10] in F32b. RF to FF32c
Stores 30 [a]. (The value of ffff0000 in hexadecimal is stored in advance in RF30 [a]) 34. If the sign flag of the CCR 35 is negative, A
Add FF32b and FF32c in LU34. Store this sum in RF30 [10]. 35. RF30 [10] is stored in FF32b. 36. Add 0 to FF32b in ALU34. This sum is stored in FF32d. 37. The value of FF32d is logically shifted to the left by 8 bits by the shifter 36. Store the shift result in FF32d. 38. The value of FF32d is logically shifted to the left by 8 bits by the shifter 36. Store the shift result in FF32d. FF32
Store RF30 [11] in c. 39. Add FF32d and FF32c in ALU34.
However, although the carry of the sum condition is stored in the CCR 35, the overflow process of the sum (setting the sum to the maximum value) is not performed. Store this sum in RF30 [11].
Reset FF32d. 40. FF32d (0), 0 and CCR3 in ALU34
Add a carry of 5. Store this sum in RF30 [13]. 41. RF30 [10] is stored in FF32b. FF32
Store RF30 [a] in c. 42. The ALU 34 calculates the logical product of the FF 32b and the FF 32c. The result is stored in FF32d. 43. 16-bit arithmetic shift of the value of FF32d to the right by the shifter 36. The shift result is stored in FF32d.
Also, RF30 [13] is stored in the FF 32c. 44. Add FF32d and FF32c in ALU34.
Store this sum in RF30 [10]. As described above, the upper word of the multiplication result (product) is RF30 [10].
The lower word is stored in RF30 [11]. By using the neuron architecture shown in FIG. 2 and the high-precision multiplication method shown in FIG. 4 and FIG. 5 in a neurocomputer that performs fixed-point and single-precision arithmetic processing in this manner, high-precision arithmetic processing becomes possible.

[0032]

As described above, the present invention has the following effects. By dividing the data that was conventionally composed of 1 word for both the multiplier and the multiplicand into multiple words and increasing the bit width, you can realize more accurate arithmetic processing than before, and add a special circuit dedicated to high precision arithmetic. Therefore, the circuit scale is not expanded and the chip area is not expanded, so that the chip cost is not increased.

Since a flip-flop and a plurality of buses are provided before and after each arithmetic unit, a value related to high precision arithmetic such as a word obtained by dividing a multiplier and a multiplicand into a plurality for high precision arithmetic can be input to an arbitrary arithmetic unit. , High accuracy calculation became possible by being able to process this. Further, by performing pipeline processing, the respective arithmetic units, for example, the ALU and the multiplier are arithmetically processed in parallel, and of course ordinary single-precision arithmetic operation is possible.
Even in the case of high precision calculation, parallel processing of high precision data using ALU or CCR can be performed during high precision multiplication as in single precision calculation. The workstation 1 in FIG.
8, the user determines the form of the neural network using the visual user interface, so that the single-precision microprogram can be uniquely determined. Similarly, if the form of the neural network is uniquely determined, the microprogram for high-precision arithmetic is also uniquely determined. Therefore, the microgenerator having the precision specified by the user is generated in the microgenerator, and the neuron corresponding to the high-precision arithmetic of the present invention is generated. By using the architecture and the high-precision arithmetic processing method, the user determines the form and arithmetic accuracy of the neural network by the visual user interface, so that the neural network operation can perform arithmetic processing with desired arithmetic accuracy.

[Brief description of drawings]

FIG. 1 shows a neurocomputer configuration diagram.

FIG. 2 shows a pipeline configuration diagram.

FIG. 3 shows a neuron block diagram.

FIG. 4 shows a conceptual diagram of a high precision multiplication method.

FIG. 5 shows a high precision multiplication flow.

FIG. 6 shows a user interface.

[Explanation of symbols]

10 ... Neurocomputer, 11 ... Control board, 12
... Neuro board, 13 ... Neural network controller, 15 ... Control storage, 16 ... Global memory, 17 ... Neuro chip, 20 ... Neuron,
30 ... Register file, 31a ... RAM, 31b ... R
AM, 32a ... Flip-flop, 32b ... Flip-flop, 32c ... Flip-flop, 32d ... Flip-flop, 32e ... Flip-flop, 33 ... Multiplier,
34 ... ALU, 35 ... Condition code register,
36 ... Shifter, 40a ... Multiplicand upper word, 40b ... Multiplicand lower word, 41a ... Multiplier upper word, 41b ... Multiplier lower word, 42 ... Partial product, 43 ... Partial product, 44 ... Partial product, 45 ... Partial product, 46 ... Multiplier lower word, 47 ... Multiplier upper word, 48a ... Partial product, 48b ... Partial product, 49
a ... product high word, 49b ... product low word.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takahiro Sakaguchi 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hiritsu Cho-LS Engineering Co., Ltd. (72) Inventor Yuji Sato Kokubunji, Tokyo 1-280, Higashi-Kengokubo, Higashi, Ltd. Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Katsunari Shibata, 1-280, Higashi-Kengokubo, Kokubunji, Tokyo (72) Inside, Central-Laboratory, Hitachi, Ltd. (72) Mitsuo Asai, 1-Higashi-Kengokubo, Kokubunji, Tokyo 280 In the Central Research Laboratory of Hitachi, Ltd. (72) Inventor Yoshihiro Kuwahara 5-22-1 Kamisuihonmachi, Kodaira-shi, Tokyo Hitachi Microcomputer System Co., Ltd. (72) Inventor ▲ Taka ▼ Hiroshi Yanagi, Tokyo 5-22-1, Mizumotocho Hitachi Microcomputer System Co., Ltd. (72) Inventor Takashi Okahashi Husband 5-22-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Microcomputer System Co., Ltd. (72) Inventor Tatsuo Ochiai 5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi Microcomputer System (72) Invention Person Mogi Keiji 5-22-1, Kamisuimotocho, Kodaira-shi, Tokyo Hitachi Microcomputer System Co., Ltd.

Claims (14)

[Claims] 1. A high-precision arithmetic processing device for performing arithmetic processing as a neuron in a neurocomputer that performs neural network operation by fixed-point and single-precision arithmetic processing, for performing arithmetic processing with higher precision than single-precision arithmetic. A high-precision arithmetic processing device comprising: a means for storing the arithmetic result of at least a multiplier, an ALU, and a shifter; and a communication means for communicating the arithmetic result. 2. A high-precision arithmetic processing device characterized in that a register file used as a work area during single-precision arithmetic processing is used as means for storing the arithmetic result according to claim 1. 3. A high-precision arithmetic processing device, wherein the output values of the multiplier, ALU, and shifter are connected to a storage device by a bus as means for communicating the arithmetic result according to claim 1. 4. A high-precision arithmetic processing device, in order to perform arithmetic processing with higher precision than single-precision arithmetic, whether a carry, overflow, sign, or value of a multiplier, a multiplicand, a partial product, an addition result, and a shift result is 0 or not. A high-precision arithmetic processing device having a condition code register (CCR) capable of detecting each of the states. 5. A high-precision arithmetic processing device characterized in that, as the CCR according to claim 4, the CCR used for detecting the state of the value fetched in the ALU during the single-precision arithmetic processing is used. 6. A high-precision arithmetic processing device that performs arithmetic processing as a neuron in a neurocomputer that performs neural network operation by fixed-point and single-precision arithmetic processing, and broadcasts the state value of the neuron from an input layer to an intermediate layer. A high-precision arithmetic processing device that equalizes the number of machine cycles required for pipeline processing at the time and when broadcasting from the middle layer to the output layer. 7. A high-precision arithmetic processing device for performing arithmetic processing as a neuron in a neurocomputer that performs neural network operation by fixed-point and single-precision arithmetic processing, wherein the neurocomputer has an architecture for performing single-precision arithmetic processing. A high-precision arithmetic processing device characterized by controlling and executing the high-precision arithmetic processing by a microprogram when performing the arithmetic processing with higher precision. 8. A high-precision arithmetic processing method for performing arithmetic processing as a neuron in a neurocomputer, which performs neural network operation by fixed-point and single-precision arithmetic processing, and which performs arithmetic processing with higher precision than single-precision arithmetic. As a high precision multiplication, even for a multiplier and a multiplicand that exceed the input bit width of the multiplier, the multiplier and the multiplicand are set to the input bit width of the single precision multiplier so that they can be multiplied by the single precision multiplier provided in the neuron in advance. A high-precision arithmetic processing method characterized by dividing each of a plurality of words within a range that does not exceed and multiplying the divided multiplier word by the divided multiplicand word to calculate a product. 9. The divided multiplier word, multiplicand word, and partial products, addition results, and shift results, which are output results of the respective arithmetic units, are stored in a storage device according to claim 8, and the stored values are stored. A high-precision arithmetic processing method characterized in that arithmetic processing is performed again by an arithmetic unit. 10. The method according to claim 8, wherein CCR is used,
A high-precision arithmetic processing method characterized in that a state of a divided multiplier word, a multiplicand word, a partial product as an output result of each arithmetic unit, an addition result, and a shift result is detected. 11. The low-order word as the least significant bit of the high-order word of the divided multiplier word and the multiplicand word when a two's complement expression is used for the multiplier and the multiplicand which are input values of the multiplier. A high-precision arithmetic processing method capable of performing high-precision multiplication by multiplying a value using a two's complement expression by adding the most significant bits of. 12. The method according to claim 8, wherein when a two's complement expression is used for a multiplier and a multiplicand which are input values of the multiplier, the divided multiplier word and the multiplicand word are arranged from the most significant bit side of each word. If the value is negative and the value is negative, the bit width of the partial product can be adjusted arbitrarily by performing sign extension in the most significant word, and control is performed so that overflow processing when adding partial products is not performed. A high-precision arithmetic processing method comprising: 13. The method according to claim 8, wherein when the two's complement representation is used for the multiplier and the multiplicand which are the input values of the multiplier, the divided multiplicand word (or multiplier word) is defined as follows.
13. The most significant bit of each divided word according to claim 12, wherein the most significant bit of the lower word is added to the least significant bit of the upper word described in 1, and the divided multiplier word (or multiplicand word) is divided. A high-precision arithmetic processing method, characterized in that processing is performed from the side so as not to carry out processing for overflow when adding partial products. 14. A high-precision arithmetic processing method for performing arithmetic processing as a neuron in a neurocomputer for performing neural network operation by fixed-point and single-precision arithmetic processing, wherein a multiplier fetches a multiplier in pipeline processing, The most significant bit of the lower word of the multiplicand is added to the least significant bit of the upper word of the multiplicand divided by the time the multiplier is input to the multiplier, and the addition state is detected by the CCR. A high-precision arithmetic processing method characterized by performing the following.