JPS6480886A - Resetting system for integrated circuit - Google Patents

Resetting system for integrated circuit

Info

Publication number
JPS6480886A
JPS6480886A JP62237217A JP23721787A JPS6480886A JP S6480886 A JPS6480886 A JP S6480886A JP 62237217 A JP62237217 A JP 62237217A JP 23721787 A JP23721787 A JP 23721787A JP S6480886 A JPS6480886 A JP S6480886A
Authority
JP
Japan
Prior art keywords
mode
reset
function module
signal
initialized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62237217A
Other languages
Japanese (ja)
Inventor
Hiroyuki Sakai
Norio Tanaka
Tsutomu Furuhashi
Yasuo Hocchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Micro Software Systems Inc
Original Assignee
Hitachi Ltd
Hitachi Micro Software Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Micro Software Systems Inc filed Critical Hitachi Ltd
Priority to JP62237217A priority Critical patent/JPS6480886A/en
Publication of JPS6480886A publication Critical patent/JPS6480886A/en
Pending legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To obtain the integrated circuit which facilitates diagnosis by adding a reset mode to an operation mode, providing a 2nd reset input terminal and initializing only internal function modules by the modes. CONSTITUTION:The operation mode is set by a mode register 1 and a function module 4 is controlled with a mode control signal 3 to realize the various operation modes. Further, the reset mode is set by the mode register 1 and a reset mode signal 6 is held at 'H' level to make the input of a function module reset signal 5 effective. Here, when the reset signal 5 is inputted through a 2nd reset input terminal 50, the function module 4 is initialized with a function module initializing signal 9, but the mode register 1 is not initialized. Thus, only the function module 4 is initialized to easily take a diagnosis.
JP62237217A 1987-09-24 1987-09-24 Resetting system for integrated circuit Pending JPS6480886A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62237217A JPS6480886A (en) 1987-09-24 1987-09-24 Resetting system for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62237217A JPS6480886A (en) 1987-09-24 1987-09-24 Resetting system for integrated circuit

Publications (1)

Publication Number Publication Date
JPS6480886A true JPS6480886A (en) 1989-03-27

Family

ID=17012117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62237217A Pending JPS6480886A (en) 1987-09-24 1987-09-24 Resetting system for integrated circuit

Country Status (1)

Country Link
JP (1) JPS6480886A (en)

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