JPS6478057A - Communication data buffer circuit - Google Patents

Abstract

PURPOSE:To prevent the leakage of reception data without forcing the change of hardware and software on a computer by providing a FIFO memory to store the reception data from a transmission/reception circuit. CONSTITUTION:When data is received, a transfer control circuit 56 supplies a control signal to the transmission/reception circuit 2, and transfers the reception data to the FIFO memory 54. The reception data is outputted from the FIFO memory 54 corresponding to the readout instruction of the computer 1. By using the FIFO memory 54, the status of a communication data buffer circuit 5 observing from a computer 1 side is different from that of the transmission/reception circuit 2, however, the status of the buffer memory in the transmission/reception circuit 2 can be corrected by substituting by the status of the FIFO memory 54 by a status register 55. In such a way, it is possible to prevent the leakage of the reception of the data while the computer is operated without applying a load of data communication on the computer.