JPS6478032A - Error location and error pattern calculation device - Google Patents

Abstract

PURPOSE:To calculate an error location and an error pattern at high speed by providing a multiplier, an adder, a 0 detector, and a divider, and performing a specific arithmetic operation. CONSTITUTION:The titled device is provided with an alpha<-1> multiplier 3, an alpha<-2> multiplier 4, an alpha<-3> multiplier 5, an alpha<-t> multiplier 6, the adders 7-9 of modulo 2, the 0 detector 10, and the divider 11. The titled calculation device calculates the values of sigma (x) and omega (x).x at a time when alpha<-0>, alpha<-1>, alpha<-2>... alpha<-(>N<-1)> and sigma, (x).x in expression II are substituted in order in the (x) of an error position polynomial sigma (x) and an error numeric value polynomial omega (x) in expression I simultaneously in the decoding processing of a reed-solomon code with code length N defined on a Galois field GF (2), and the error location jk is detected from the 0 detector 10, and simultaneously, the error pattern Yjk is outputted from the divider 11 of the Galois field. In expression 1, (l) represents the num ber, and (alpha) the original dimention of a GF(2<m>). In such a way, it is possible to find the error location and the error pattern simultaneously and in a short time.