JPS6477323A - Optional calibration type analog/digital conversion system - Google Patents
Optional calibration type analog/digital conversion systemInfo
- Publication number
- JPS6477323A JPS6477323A JP23406787A JP23406787A JPS6477323A JP S6477323 A JPS6477323 A JP S6477323A JP 23406787 A JP23406787 A JP 23406787A JP 23406787 A JP23406787 A JP 23406787A JP S6477323 A JPS6477323 A JP S6477323A
- Authority
- JP
- Japan
- Prior art keywords
- conv
- cycle
- cal
- error detecting
- calibration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE:To optionally update error data for self-calibration by using three self-calibration type AD converting means having the same constitution, coupling two of them to allocate the coupled means to a conversion cycle and the residual one to an error detecting cycle. CONSTITUTION:Three self-calibration type AD converters 11-13 are used and a conversion cycle Conv.H for high-order bits, a conversion cycle Conv.L for low-order bits and an error detecting cycle Cal. are allocated to respective AD converters and respective cycles are rotated in the order of 'Cal.', 'Conv.H' and 'Conv.L'. When the AD converter allocated to the conversion cycle Conv.L for low-order bits is in a 'discharging' period, the error detecting cycle Cal. is allocated to the converter. When the completion of calibration for all bits is impossible by one error detecting cycle Cal., the operation is divided into plural times.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23406787A JPS6477323A (en) | 1987-09-18 | 1987-09-18 | Optional calibration type analog/digital conversion system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23406787A JPS6477323A (en) | 1987-09-18 | 1987-09-18 | Optional calibration type analog/digital conversion system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6477323A true JPS6477323A (en) | 1989-03-23 |
Family
ID=16965071
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23406787A Pending JPS6477323A (en) | 1987-09-18 | 1987-09-18 | Optional calibration type analog/digital conversion system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6477323A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008131298A (en) * | 2006-11-20 | 2008-06-05 | Fyuutorekku:Kk | Analog/digital conversion device, and analog/digital conversion correction method |
JP2010045723A (en) * | 2008-08-18 | 2010-02-25 | Fujitsu Ltd | Digital-to-analog converter |
JP2011049746A (en) * | 2009-08-26 | 2011-03-10 | Nec Corp | A/d converter |
-
1987
- 1987-09-18 JP JP23406787A patent/JPS6477323A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008131298A (en) * | 2006-11-20 | 2008-06-05 | Fyuutorekku:Kk | Analog/digital conversion device, and analog/digital conversion correction method |
JP2010045723A (en) * | 2008-08-18 | 2010-02-25 | Fujitsu Ltd | Digital-to-analog converter |
JP2011049746A (en) * | 2009-08-26 | 2011-03-10 | Nec Corp | A/d converter |
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