JPS6474881A - Recording and reproducing method - Google Patents

Recording and reproducing method

Info

Publication number
JPS6474881A
JPS6474881A JP62232970A JP23297087A JPS6474881A JP S6474881 A JPS6474881 A JP S6474881A JP 62232970 A JP62232970 A JP 62232970A JP 23297087 A JP23297087 A JP 23297087A JP S6474881 A JPS6474881 A JP S6474881A
Authority
JP
Japan
Prior art keywords
converter
output
video signal
level
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62232970A
Other languages
Japanese (ja)
Inventor
Hitoshi Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP62232970A priority Critical patent/JPS6474881A/en
Publication of JPS6474881A publication Critical patent/JPS6474881A/en
Pending legal-status Critical Current

Links

Landscapes

  • Television Signal Processing For Recording (AREA)

Abstract

PURPOSE:To execute the faithful reproducing of a part in which the amplitude of a video signal is small by amplifying an analog signal, which is obtained by a gain to correspond to an amplifying gain at a digitalizing in each prescribed section and equalizing the peak level of an input video signal to the maximum level of the input level range of an A/D converter. CONSTITUTION:The input video signal is inputted through an LPF 1 to analog switches 16-19, which are controlled by a system control circuit 20 of a variable resistance attenuator 15, and the output of the attenuator 15 is inputted through an amplifier 4 and a clamp 5 to an A/D converter 6. The peak level of the output of this converter 6 is detected by a peak level detecting circuit 21, added to a memory 22 and temporarily held and the switches 16-19 are controlled based on the control of the circuit 20. Then, the output of the converter 6 is stored to a memory 7 and the output is D/A converted and inputted to a variable resistance attenuator 25. Then, the peak level of the input video signal is equalized to the maximum level of the input level range of the converter 6.
JP62232970A 1987-09-17 1987-09-17 Recording and reproducing method Pending JPS6474881A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62232970A JPS6474881A (en) 1987-09-17 1987-09-17 Recording and reproducing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62232970A JPS6474881A (en) 1987-09-17 1987-09-17 Recording and reproducing method

Publications (1)

Publication Number Publication Date
JPS6474881A true JPS6474881A (en) 1989-03-20

Family

ID=16947735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62232970A Pending JPS6474881A (en) 1987-09-17 1987-09-17 Recording and reproducing method

Country Status (1)

Country Link
JP (1) JPS6474881A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07170306A (en) * 1993-12-15 1995-07-04 Nec Corp Demodulator
JP2008269368A (en) * 2007-04-21 2008-11-06 Nidec Sankyo Corp Medium processing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07170306A (en) * 1993-12-15 1995-07-04 Nec Corp Demodulator
JP2008269368A (en) * 2007-04-21 2008-11-06 Nidec Sankyo Corp Medium processing device

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