JPS6474471A - Diagnostic system - Google Patents

Diagnostic system

Info

Publication number
JPS6474471A
JPS6474471A JP62233347A JP23334787A JPS6474471A JP S6474471 A JPS6474471 A JP S6474471A JP 62233347 A JP62233347 A JP 62233347A JP 23334787 A JP23334787 A JP 23334787A JP S6474471 A JPS6474471 A JP S6474471A
Authority
JP
Japan
Prior art keywords
driver
inputted
clock
bus fight
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62233347A
Other languages
Japanese (ja)
Inventor
Yoshihiro Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62233347A priority Critical patent/JPS6474471A/en
Publication of JPS6474471A publication Critical patent/JPS6474471A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To take measures to select a higher-priority signal and to preclude a bus fight completely by detecting conditions by a bus fight detecting means previously. CONSTITUTION:Two drive signals 14 and 24 supplied from a testing device 3 are branched and inputted to a NAND circuit 31 in the bus fight condition detection part 6 and when the simultaneous generation of both signals is detected, a low level is outputted to one input terminal of an AND circuit 32 in a priority selection part 7 while a clock 15 is inhibited from being inputted to the other input terminal. Its output is inputted to the clock terminal of a flip-flop 13 to stop the driver signals from being sent out to a driver 11. Therefore, the driver signal 24 is selected preferentially and outputted through a flip-flop 23 with a clock 25 to drive a driver 21. Consequently, the bus fight is precluded completely.
JP62233347A 1987-09-17 1987-09-17 Diagnostic system Pending JPS6474471A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62233347A JPS6474471A (en) 1987-09-17 1987-09-17 Diagnostic system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62233347A JPS6474471A (en) 1987-09-17 1987-09-17 Diagnostic system

Publications (1)

Publication Number Publication Date
JPS6474471A true JPS6474471A (en) 1989-03-20

Family

ID=16953723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62233347A Pending JPS6474471A (en) 1987-09-17 1987-09-17 Diagnostic system

Country Status (1)

Country Link
JP (1) JPS6474471A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008256253A (en) * 2007-04-04 2008-10-23 Toyota Motor Corp Heat exchanger and manufacturing method of heat exchanger

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008256253A (en) * 2007-04-04 2008-10-23 Toyota Motor Corp Heat exchanger and manufacturing method of heat exchanger

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