JPS6473594A - Multiport memory - Google Patents

Multiport memory

Info

Publication number
JPS6473594A
JPS6473594A JP62231402A JP23140287A JPS6473594A JP S6473594 A JPS6473594 A JP S6473594A JP 62231402 A JP62231402 A JP 62231402A JP 23140287 A JP23140287 A JP 23140287A JP S6473594 A JPS6473594 A JP S6473594A
Authority
JP
Japan
Prior art keywords
word line
signal generating
control signal
signals
generating device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62231402A
Other languages
Japanese (ja)
Inventor
Shintaro Shibata
Kanichi Endo
Hirotoshi Sawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP62231402A priority Critical patent/JPS6473594A/en
Publication of JPS6473594A publication Critical patent/JPS6473594A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To accurately constitute a small-sized titled memory by reducing the word lines and the bit lines of a memory cell array. CONSTITUTION:The plural (p) pieces of word line address signals WAa1-WAap are inputted to a word line selecting driving device, bit line address signals BAa1-BAap are inputted to a control signal generating device CSa and the word line address signals WAa1-WAap and the bit line signals BAa1-BAap are inputted to a control signal generating device CCa successively with number of times (q). Control signals WGSa1, WGSa2...WGSap for a word line decoding output gate are successively outputted from the control signal generating device CCa to a word line selecting driving device WSDa, control signals BGSa1, BGSa2-BGSap for a bit line selection are successively outputted to the control signal generating device CSa and control signals IDOSa1, IDOSa2...IDOSap for an information detection/amplification are successively outputted to an information reader with number of times (q). Thus, the miniaturization of the memory is attained accurately.
JP62231402A 1987-09-16 1987-09-16 Multiport memory Pending JPS6473594A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62231402A JPS6473594A (en) 1987-09-16 1987-09-16 Multiport memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62231402A JPS6473594A (en) 1987-09-16 1987-09-16 Multiport memory

Publications (1)

Publication Number Publication Date
JPS6473594A true JPS6473594A (en) 1989-03-17

Family

ID=16923042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62231402A Pending JPS6473594A (en) 1987-09-16 1987-09-16 Multiport memory

Country Status (1)

Country Link
JP (1) JPS6473594A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5502683A (en) * 1993-04-20 1996-03-26 International Business Machines Corporation Dual ported memory with word line access control

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5502683A (en) * 1993-04-20 1996-03-26 International Business Machines Corporation Dual ported memory with word line access control

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