JPS647202A - Pc input/output card - Google Patents

Pc input/output card

Info

Publication number
JPS647202A
JPS647202A JP16360587A JP16360587A JPS647202A JP S647202 A JPS647202 A JP S647202A JP 16360587 A JP16360587 A JP 16360587A JP 16360587 A JP16360587 A JP 16360587A JP S647202 A JPS647202 A JP S647202A
Authority
JP
Japan
Prior art keywords
circuit
output
input
logical circuit
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16360587A
Other languages
Japanese (ja)
Inventor
Fuyuhiko Yoshikura
Takayuki Ishihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Motor Corp
Original Assignee
Toyota Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Motor Corp filed Critical Toyota Motor Corp
Priority to JP16360587A priority Critical patent/JPS647202A/en
Publication of JPS647202A publication Critical patent/JPS647202A/en
Pending legal-status Critical Current

Links

Landscapes

  • Programmable Controllers (AREA)

Abstract

PURPOSE:To improve a switching responsiveness and to eliminate the variance by mounting an input part and an output part into one car and mounting a logical circuit into the internal part. CONSTITUTION:An input part 1 connected to the input circuit of a programmable controller PC 3 and an output part 2 connected to an output circuit are mounted on one card and between the input part 1 and the output part 2, logical circuits 10, 11 and 12 which go to ON under the constant conditions are mounted. Namely, the logical circuit 10 is the circuit to output when all the inputs of relays R4 and R5 are a relay W2 are executed, and the logical circuit 11 is the circuit to output when either of the outputs of the logical circuit 10 or a relay W3 is executed. Further, the logical circuit 12 outputs when both outputs of the logical circuit 11 and a relay W4 are executed. Thus, the time lag due to the point of time to step on limit switches 4 and 5 and the variance can be eliminated.
JP16360587A 1987-06-30 1987-06-30 Pc input/output card Pending JPS647202A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16360587A JPS647202A (en) 1987-06-30 1987-06-30 Pc input/output card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16360587A JPS647202A (en) 1987-06-30 1987-06-30 Pc input/output card

Publications (1)

Publication Number Publication Date
JPS647202A true JPS647202A (en) 1989-01-11

Family

ID=15777105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16360587A Pending JPS647202A (en) 1987-06-30 1987-06-30 Pc input/output card

Country Status (1)

Country Link
JP (1) JPS647202A (en)

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