JPS6471286A - Highly stable synchronizing oscillator - Google Patents

Highly stable synchronizing oscillator

Info

Publication number
JPS6471286A
JPS6471286A JP22646887A JP22646887A JPS6471286A JP S6471286 A JPS6471286 A JP S6471286A JP 22646887 A JP22646887 A JP 22646887A JP 22646887 A JP22646887 A JP 22646887A JP S6471286 A JPS6471286 A JP S6471286A
Authority
JP
Japan
Prior art keywords
oscillator
pll circuit
highly stable
inputted
pass filter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22646887A
Other languages
Japanese (ja)
Inventor
Nobuo Furuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP22646887A priority Critical patent/JPS6471286A/en
Publication of JPS6471286A publication Critical patent/JPS6471286A/en
Pending legal-status Critical Current

Links

Landscapes

  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE:To constitute a small sized and inexpensive highly stable synchronizing oscillator by providing an intermittent timer and a control voltage holding circuit of a voltage controlled crystal oscillator to a PLL circuit of a synchronizing oscillator. CONSTITUTION:A subcarrier from input terminals 1, 2 is amplified by amplifiers 3, 4 and inputted to a balance mixer 5. The output of the balance mixer 5 is given to a distributer 6, a high pass filter 7 and a low pass filter 8 and the result is inputted to a PLL circuit 18 through the switch 15. The PLL circuit 18 has the intermission timer 25 and a control voltage holding circuit 24 of a voltage controlled oscillator 20 to generate a stable output frequency.
JP22646887A 1987-09-11 1987-09-11 Highly stable synchronizing oscillator Pending JPS6471286A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22646887A JPS6471286A (en) 1987-09-11 1987-09-11 Highly stable synchronizing oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22646887A JPS6471286A (en) 1987-09-11 1987-09-11 Highly stable synchronizing oscillator

Publications (1)

Publication Number Publication Date
JPS6471286A true JPS6471286A (en) 1989-03-16

Family

ID=16845572

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22646887A Pending JPS6471286A (en) 1987-09-11 1987-09-11 Highly stable synchronizing oscillator

Country Status (1)

Country Link
JP (1) JPS6471286A (en)

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