JPS6468837A - Developing system for binary addition - Google Patents

Developing system for binary addition

Info

Publication number
JPS6468837A
JPS6468837A JP62227621A JP22762187A JPS6468837A JP S6468837 A JPS6468837 A JP S6468837A JP 62227621 A JP62227621 A JP 62227621A JP 22762187 A JP22762187 A JP 22762187A JP S6468837 A JPS6468837 A JP S6468837A
Authority
JP
Japan
Prior art keywords
digits
quaternaries
object program
temporary
operands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62227621A
Other languages
Japanese (ja)
Inventor
Koji Fukuda
Yoshio Yukie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62227621A priority Critical patent/JPS6468837A/en
Publication of JPS6468837A publication Critical patent/JPS6468837A/en
Pending legal-status Critical Current

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  • Devices For Executing Special Programs (AREA)

Abstract

PURPOSE:To improve the efficiency of an object program by holding the number of digits of an area, where the intermediate result of binary addition is stored, as not the number of bytes but a decimal number. CONSTITUTION:A front end means 2 which analyzes an arithmetic expression in a source program to an intermediate text of quaternaries consisting of an operator, two operands, and an intermediate temporary and an intermediate digit number determining means 4 which determines the number of digits of the intermediate temporary with the decimal precision on the basis of the number of digits of operands are provided. A code generating means 6 is provided which generates an object code from respective quaternaries in the intermediate text while developing quaternaries to combinations with basic instructions or other hardware instructions on the basis of the determined number of digits of the intermediate temporary. A rate of development of addition in the object program of the arithmetic expression including plural additions to basic instructions is raised to improve the efficiency of the object program.
JP62227621A 1987-09-10 1987-09-10 Developing system for binary addition Pending JPS6468837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62227621A JPS6468837A (en) 1987-09-10 1987-09-10 Developing system for binary addition

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62227621A JPS6468837A (en) 1987-09-10 1987-09-10 Developing system for binary addition

Publications (1)

Publication Number Publication Date
JPS6468837A true JPS6468837A (en) 1989-03-14

Family

ID=16863799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62227621A Pending JPS6468837A (en) 1987-09-10 1987-09-10 Developing system for binary addition

Country Status (1)

Country Link
JP (1) JPS6468837A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6155738A (en) * 1984-08-27 1986-03-20 Fujitsu Ltd Determining system of operation mode
JPS62137637A (en) * 1985-12-11 1987-06-20 Nec Corp Arithmetic accuracy setting system in language processing system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6155738A (en) * 1984-08-27 1986-03-20 Fujitsu Ltd Determining system of operation mode
JPS62137637A (en) * 1985-12-11 1987-06-20 Nec Corp Arithmetic accuracy setting system in language processing system

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