JPS6468668A - Data compressor - Google Patents

Data compressor

Info

Publication number
JPS6468668A
JPS6468668A JP62223956A JP22395687A JPS6468668A JP S6468668 A JPS6468668 A JP S6468668A JP 62223956 A JP62223956 A JP 62223956A JP 22395687 A JP22395687 A JP 22395687A JP S6468668 A JPS6468668 A JP S6468668A
Authority
JP
Japan
Prior art keywords
lfsr
data
polynomial
feedback
fault
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62223956A
Other languages
Japanese (ja)
Inventor
Naohiro Hasegawa
Hiroshi Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Ltd
Hitachi Tohbu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Tohbu Semiconductor Ltd filed Critical Hitachi Ltd
Priority to JP62223956A priority Critical patent/JPS6468668A/en
Publication of JPS6468668A publication Critical patent/JPS6468668A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce a fault overlook rate by composing the data compressor of a linear feedback shift register whose feedback position can be selected in plural ways. CONSTITUTION:When a selection control signal SC is held at high level, an exclusive OR circuit EXOR2 ORs the output signals of data latch circuits DL3 and DL4 and the linear feedback shift register LFSR employs a generating polynomial which has the output terminals of the circuits DL3 and DL4 as feedback positions. When the signal SC is lowered to low level, a polynomial which has the output terminals of the DLs 2 and 4 as feedback positions is employed. Then when test input data Din is supplied to the LFSR, the data is shifted cyclically for the current generating polynomial, and compressed into four bits and held. Thus, Din is supplied to the LFSR repeatedly under the different generating polynomials and the fault overlook rate obtained by the (m)-stage LFSR is reduced to 1/2<2m>.
JP62223956A 1987-09-09 1987-09-09 Data compressor Pending JPS6468668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62223956A JPS6468668A (en) 1987-09-09 1987-09-09 Data compressor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62223956A JPS6468668A (en) 1987-09-09 1987-09-09 Data compressor

Publications (1)

Publication Number Publication Date
JPS6468668A true JPS6468668A (en) 1989-03-14

Family

ID=16806330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62223956A Pending JPS6468668A (en) 1987-09-09 1987-09-09 Data compressor

Country Status (1)

Country Link
JP (1) JPS6468668A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011520178A (en) * 2008-04-14 2011-07-14 シーメンス アクチエンゲゼルシヤフト Bit sequence generation method and apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011520178A (en) * 2008-04-14 2011-07-14 シーメンス アクチエンゲゼルシヤフト Bit sequence generation method and apparatus
US8531247B2 (en) 2008-04-14 2013-09-10 Siemens Aktiengesellschaft Device and method for generating a random bit sequence

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