JPS6468070A - Clamping circuit - Google Patents

Clamping circuit

Info

Publication number
JPS6468070A
JPS6468070A JP62224507A JP22450787A JPS6468070A JP S6468070 A JPS6468070 A JP S6468070A JP 62224507 A JP62224507 A JP 62224507A JP 22450787 A JP22450787 A JP 22450787A JP S6468070 A JPS6468070 A JP S6468070A
Authority
JP
Japan
Prior art keywords
level
synchronizing signal
conjugated
value
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62224507A
Other languages
Japanese (ja)
Inventor
Seiichi Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62224507A priority Critical patent/JPS6468070A/en
Publication of JPS6468070A publication Critical patent/JPS6468070A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To control the DC level of a luminance signal or a conjugated video signal even when a synchronizing signal can not be separated, by varying the DC level so that the target value of clamping level and an output from a switching means coincide with each other. CONSTITUTION:The leading value on the synchronizing signal side of a conjugated video signal in a regulate period so that at least one or more synchronizing signal is included is included, is detected, held, and updated, however, in case a horizontal synchronizing signal HD is not separated, the DC level of an input conjugated video signal is varied so that said value and a clamping level coincide with each other, and thus the DC level at the leading end of a synchronizing signal is controlled to be constant. Since said detection of the leading value on the synchronizing signal side is executed after subjecting an input conjugated video signal to a low-pass filter 23, the difference between said value and a true synchronizing signal leading value caused by high frequency noise component can be eliminated. As a result, even when a horizontal synchronizing signal is not separated, the DC level of an input conjugated video signal can be controlled.
JP62224507A 1987-09-08 1987-09-08 Clamping circuit Pending JPS6468070A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62224507A JPS6468070A (en) 1987-09-08 1987-09-08 Clamping circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62224507A JPS6468070A (en) 1987-09-08 1987-09-08 Clamping circuit

Publications (1)

Publication Number Publication Date
JPS6468070A true JPS6468070A (en) 1989-03-14

Family

ID=16814884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62224507A Pending JPS6468070A (en) 1987-09-08 1987-09-08 Clamping circuit

Country Status (1)

Country Link
JP (1) JPS6468070A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04319870A (en) * 1991-04-18 1992-11-10 Fujitsu General Ltd Dc level detecting circuit
JP2012088052A (en) * 2005-07-14 2012-05-10 Access Business Group Internatl Llc Method of setting reference voltage for sensor in air treatment system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04319870A (en) * 1991-04-18 1992-11-10 Fujitsu General Ltd Dc level detecting circuit
JP2012088052A (en) * 2005-07-14 2012-05-10 Access Business Group Internatl Llc Method of setting reference voltage for sensor in air treatment system

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