JPS57197986A - Color signal processing circuit - Google Patents
Color signal processing circuitInfo
- Publication number
- JPS57197986A JPS57197986A JP8302681A JP8302681A JPS57197986A JP S57197986 A JPS57197986 A JP S57197986A JP 8302681 A JP8302681 A JP 8302681A JP 8302681 A JP8302681 A JP 8302681A JP S57197986 A JPS57197986 A JP S57197986A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- delay line
- amplifier
- chrominance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/642—Multi-standard receivers
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Processing Of Color Television Signals (AREA)
Abstract
PURPOSE:To control automatically whether a chrominance signal of the PAL system is switched to be supplied to a 1H delay line and an adding and subtracting circuit or not, by providing a switching circuit consisting of two transistors (TRs) in a chrominance processing circuit common to the NTSC system and the PAL system. CONSTITUTION:A switching circuit 63 controlled by the output of a discriminating circuit 62 of the video signal system is provided between an amplifier 10 of a common processing circuit for chrominance signals of color video signal of the PAL system and the NTSC system and a delay line 64 having a delay quantity of one horizontal period as well as an adding and subtracting circuit 65 to which the output the delay line 64 is supplied. The switching circuit 63 is provided with a TR Q2, which receives the chrominance signal from the amplifier 10 by the base and supplies the collector output to the delay line 64 and supplies the emitter output to the adding and subtracting circuit 65, and a TR Q1 which receives the chrominance signal from the amplifier 10 and the output of the circuit 52 by the base and has the emitter connected to the emitter of the TR Q2 and has the collector grounded, thus controlling automatically whether the chrominance signal of the PAL system from the amplifier 10 is switched to be supplied to the delay line 64 and the adding and subtracting circuit 65 or not.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8302681A JPS57197986A (en) | 1981-05-29 | 1981-05-29 | Color signal processing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8302681A JPS57197986A (en) | 1981-05-29 | 1981-05-29 | Color signal processing circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57197986A true JPS57197986A (en) | 1982-12-04 |
Family
ID=13790719
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8302681A Pending JPS57197986A (en) | 1981-05-29 | 1981-05-29 | Color signal processing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57197986A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4658284A (en) * | 1984-01-11 | 1987-04-14 | Canon Kabushiki Kaisha | Image forming apparatus |
JPH06886U (en) * | 1991-11-12 | 1994-01-11 | 古河電気工業株式会社 | Rigid train line mount connection |
-
1981
- 1981-05-29 JP JP8302681A patent/JPS57197986A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4658284A (en) * | 1984-01-11 | 1987-04-14 | Canon Kabushiki Kaisha | Image forming apparatus |
JPH06886U (en) * | 1991-11-12 | 1994-01-11 | 古河電気工業株式会社 | Rigid train line mount connection |
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