JPS5679593A - Color television receiver - Google Patents
Color television receiverInfo
- Publication number
- JPS5679593A JPS5679593A JP15701879A JP15701879A JPS5679593A JP S5679593 A JPS5679593 A JP S5679593A JP 15701879 A JP15701879 A JP 15701879A JP 15701879 A JP15701879 A JP 15701879A JP S5679593 A JPS5679593 A JP S5679593A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- delay
- addition
- subtraction
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N11/00—Colour television systems
- H04N11/06—Transmission systems characterised by the manner in which the individual colour picture signal components are combined
- H04N11/12—Transmission systems characterised by the manner in which the individual colour picture signal components are combined using simultaneous signals only
- H04N11/14—Transmission systems characterised by the manner in which the individual colour picture signal components are combined using simultaneous signals only in which one signal, modulated in phase and amplitude, conveys colour information and a second signal conveys brightness information, e.g. NTSC-system
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Color Television Systems (AREA)
- Processing Of Color Television Signals (AREA)
Abstract
PURPOSE:To avoid addition/subtraction output between a 1H delay signal and a nondelay signal to give an undesirable effect on the succeeding circuit, by avoiding to give a delay signal from 1H delay line for a desired period. CONSTITUTION:The means 22 is provided, to avoid giving the 1H delay signal to the linewhich is undesirable the addition/subtraction output between the 1H delay signal and the nondelay signal. For example, the line undesirable the output of addition/subtraction is the line inserted with the VIR signal, and no signal is input to the delay line 7 and the VIR signal only as a nondelay signal is given to the luminance signal and the chroma signal circuit 10 through the addition and subtraction circuits 8 and 9.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15701879A JPS5679593A (en) | 1979-12-03 | 1979-12-03 | Color television receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15701879A JPS5679593A (en) | 1979-12-03 | 1979-12-03 | Color television receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5679593A true JPS5679593A (en) | 1981-06-30 |
Family
ID=15640377
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15701879A Pending JPS5679593A (en) | 1979-12-03 | 1979-12-03 | Color television receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5679593A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6472681A (en) * | 1987-09-08 | 1989-03-17 | Zenith Electronics Corp | Image processor |
-
1979
- 1979-12-03 JP JP15701879A patent/JPS5679593A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6472681A (en) * | 1987-09-08 | 1989-03-17 | Zenith Electronics Corp | Image processor |
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