JPS6467943A - Laminated semiconductor device - Google Patents

Laminated semiconductor device

Info

Publication number
JPS6467943A
JPS6467943A JP22502287A JP22502287A JPS6467943A JP S6467943 A JPS6467943 A JP S6467943A JP 22502287 A JP22502287 A JP 22502287A JP 22502287 A JP22502287 A JP 22502287A JP S6467943 A JPS6467943 A JP S6467943A
Authority
JP
Japan
Prior art keywords
conductors
semiconductor layers
layers
crosstalking
electrically isolated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22502287A
Other languages
Japanese (ja)
Inventor
Masatoshi Kimura
Toshio Kumamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP22502287A priority Critical patent/JPS6467943A/en
Publication of JPS6467943A publication Critical patent/JPS6467943A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent adjacent semiconductors from crosstalking and a noise from transmitting therebetween by providing a plurality of planar conductors electrically isolated from each other in insulating layers of the same hierarchy, and connecting the conductors only to one of two adjacent semiconductor layers. CONSTITUTION:First and second conductors 14a, 14b and 24a, 24b are divided on the same plane in the same hierarchy while being electrically isolated from each other in respective hierarchies of insulation layers 2a and 2b, and the conductors 14a, 14b, 24a, 24b are connected to only wirings of one of adjacent semiconductor layers 3a, 3b; 3b, 3a. The conductors 14a, 14b, 24a, 24b are formed in a pectinated planar shape. Since the first and second conductors 14a, 14b; 24a, 24b are respectively held at constant voltages, it prevents the semiconductor layers from crosstalking therebetween by an electrostatic shielding effect.
JP22502287A 1987-09-08 1987-09-08 Laminated semiconductor device Pending JPS6467943A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22502287A JPS6467943A (en) 1987-09-08 1987-09-08 Laminated semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22502287A JPS6467943A (en) 1987-09-08 1987-09-08 Laminated semiconductor device

Publications (1)

Publication Number Publication Date
JPS6467943A true JPS6467943A (en) 1989-03-14

Family

ID=16822843

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22502287A Pending JPS6467943A (en) 1987-09-08 1987-09-08 Laminated semiconductor device

Country Status (1)

Country Link
JP (1) JPS6467943A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5196920A (en) * 1992-04-21 1993-03-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device for limiting capacitive coupling between adjacent circuit blocks
JP2020120046A (en) * 2019-01-25 2020-08-06 日本放送協会 Laminated semiconductor device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5196920A (en) * 1992-04-21 1993-03-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device for limiting capacitive coupling between adjacent circuit blocks
JP2020120046A (en) * 2019-01-25 2020-08-06 日本放送協会 Laminated semiconductor device and method for manufacturing the same

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