JPS6466693A - Display device - Google Patents

Display device

Info

Publication number
JPS6466693A
JPS6466693A JP62223445A JP22344587A JPS6466693A JP S6466693 A JPS6466693 A JP S6466693A JP 62223445 A JP62223445 A JP 62223445A JP 22344587 A JP22344587 A JP 22344587A JP S6466693 A JPS6466693 A JP S6466693A
Authority
JP
Japan
Prior art keywords
output
address
character
cpu
raster
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62223445A
Other languages
Japanese (ja)
Inventor
Hisahiro Koga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62223445A priority Critical patent/JPS6466693A/en
Publication of JPS6466693A publication Critical patent/JPS6466693A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

PURPOSE: To eliminate screen disturbance by switching the character code of VRAM output and the raster address of CRTC output to those specified and latched by CPU and inputting them during one display cycle period on the character generation address. CONSTITUTION: The character code of VRAM 2 output and the raster address of CRTC 1 output are switched to the character code and the raster address of a latch 5 output holding CPU output data, by switches 7, 8 through a signal synchronized with the control clock of CRTC, with the switched output inputted in the address of a character generator 3. In addition, the output font data of the character generator 3 is latched by a data buffer 9 with timing corresponding to the code and raster specified by CPU, and outputted to CPU pass. The output font data of the character generator 3 is outputted as a VIDEO signal in a P/S conversion circuit.
JP62223445A 1987-09-07 1987-09-07 Display device Pending JPS6466693A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62223445A JPS6466693A (en) 1987-09-07 1987-09-07 Display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62223445A JPS6466693A (en) 1987-09-07 1987-09-07 Display device

Publications (1)

Publication Number Publication Date
JPS6466693A true JPS6466693A (en) 1989-03-13

Family

ID=16798251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62223445A Pending JPS6466693A (en) 1987-09-07 1987-09-07 Display device

Country Status (1)

Country Link
JP (1) JPS6466693A (en)

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