JPS6462929A - Repeater - Google Patents

Repeater

Info

Publication number
JPS6462929A
JPS6462929A JP21997487A JP21997487A JPS6462929A JP S6462929 A JPS6462929 A JP S6462929A JP 21997487 A JP21997487 A JP 21997487A JP 21997487 A JP21997487 A JP 21997487A JP S6462929 A JPS6462929 A JP S6462929A
Authority
JP
Japan
Prior art keywords
signal
stage
fault
circuit
synchronizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21997487A
Other languages
Japanese (ja)
Inventor
Masahiro Nakajima
Seiji Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP21997487A priority Critical patent/JPS6462929A/en
Publication of JPS6462929A publication Critical patent/JPS6462929A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain normal restoration after fault recovery in a short time, by selecting a synchronizing signal from a pre-stage as it is as an output in response to the detection output of a fault when a multi-stage repeater detects the fault of a means synchronizing with an input signal from the pre-stage. CONSTITUTION:An input signal 1 from the pre-stage is given to a frame synchronizing circuit 100 and a switching circuit 102 of a repeater 7. The frame synchronizing circuit 100 takes frame synchronization with the input signal 1 to extract a redundancy signal or an auxiliary signal and inserts an auxiliary signal 2. When no error exists in the circuit 100, the output 6 of the synchronizing circuit 100 is sent to the post-stage via a switching circuit 102. When a fault detection circuit 101 uses a monitoring signal 3 to detect the fault of the circuit 100, the switching signal 5 is sent to the switching circuit 102 to output the input signal 1 from the prestage to the post-stage as it is. When the fault is recovered, the state is restored into the initial state and the signal 6 is outputted (4) to the post-stage. Thus, the time of the frame synchronization in all repeaters at the restoration of fault is shortened.
JP21997487A 1987-09-02 1987-09-02 Repeater Pending JPS6462929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21997487A JPS6462929A (en) 1987-09-02 1987-09-02 Repeater

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21997487A JPS6462929A (en) 1987-09-02 1987-09-02 Repeater

Publications (1)

Publication Number Publication Date
JPS6462929A true JPS6462929A (en) 1989-03-09

Family

ID=16743944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21997487A Pending JPS6462929A (en) 1987-09-02 1987-09-02 Repeater

Country Status (1)

Country Link
JP (1) JPS6462929A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5784645A (en) * 1980-11-17 1982-05-27 Fujitsu Ltd By-pass circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5784645A (en) * 1980-11-17 1982-05-27 Fujitsu Ltd By-pass circuit

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