JPS6461986A - Plating of printed board - Google Patents

Plating of printed board

Info

Publication number
JPS6461986A
JPS6461986A JP21986587A JP21986587A JPS6461986A JP S6461986 A JPS6461986 A JP S6461986A JP 21986587 A JP21986587 A JP 21986587A JP 21986587 A JP21986587 A JP 21986587A JP S6461986 A JPS6461986 A JP S6461986A
Authority
JP
Japan
Prior art keywords
electrolyte
board
electrolytic copper
electrode
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21986587A
Other languages
Japanese (ja)
Inventor
Osamu Kasai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21986587A priority Critical patent/JPS6461986A/en
Publication of JPS6461986A publication Critical patent/JPS6461986A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PURPOSE:To form an electrolytic copper plated layer of a sufficient thickness in a through hole as well as selectively only on one side of a substrate by a method wherein an electrode sheet is provided opposite to the formed resist pattern side of a printed board while the substrate is plated meeting the requirements for a specified content of copper sulfate in electrolyte and a specified current density between the substrate and the electrode. CONSTITUTION:A printed board 4 with a through hole 3 made and resist patterns 6 formed on one side is immersed in electrolyte (electrolytic copper plating solution) 11. This electrolyte of 1l is composed of 270-330gr of copper sulfate (CuSO4.5H2O), 100gr of H2SO4 in 98 weight %, chlorine ion concentration in 50ppm with specified amount of salt added to said plating bath materials melted in water as solvent. Next, the board 4 and electrodes are impressed with direct current making the current density of electrolyte 55-65mA/cm<2> assuming the board 4 as negative electrode side while a copper electrode 9 provided opposite to the board side whereon the resist patterns 6 are formed as positive electrode side. Through these procedures, an electrolytic copper plated layer 10 in sufficient thickness can be formed in the through hole while the electrolytic copper plated layer 10 can be formed selectively only on one side whereon the resist patterns 6 are formed.
JP21986587A 1987-09-01 1987-09-01 Plating of printed board Pending JPS6461986A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21986587A JPS6461986A (en) 1987-09-01 1987-09-01 Plating of printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21986587A JPS6461986A (en) 1987-09-01 1987-09-01 Plating of printed board

Publications (1)

Publication Number Publication Date
JPS6461986A true JPS6461986A (en) 1989-03-08

Family

ID=16742269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21986587A Pending JPS6461986A (en) 1987-09-01 1987-09-01 Plating of printed board

Country Status (1)

Country Link
JP (1) JPS6461986A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000049655A1 (en) * 1999-02-18 2000-08-24 Seiko Epson Corporation Semiconductor device, circuit board, method of manufacturing circuit board, and electronic device
JP2006188745A (en) * 2004-12-30 2006-07-20 Samsung Electro Mech Co Ltd Fill plated structure of inner via hole and manufacturing method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000049655A1 (en) * 1999-02-18 2000-08-24 Seiko Epson Corporation Semiconductor device, circuit board, method of manufacturing circuit board, and electronic device
US6798058B1 (en) 1999-02-18 2004-09-28 Seiko Epson Corporation Semiconductor device, mounting and method of manufacturing mounting substrate, circuit board, and electronic instrument
US7163613B2 (en) 1999-02-18 2007-01-16 Seiko Epson Corporation Method of manufacturing a semiconductor device by forming plating layers having differing thicknesses
US8110245B2 (en) 1999-02-18 2012-02-07 Seiko Epson Corporation Semiconductor device, mounting substrate and method of manufacturing mounting substrate, circuit board, and electronic instrument
JP2006188745A (en) * 2004-12-30 2006-07-20 Samsung Electro Mech Co Ltd Fill plated structure of inner via hole and manufacturing method thereof

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