JPS6461124A - Crc circuit - Google Patents

Crc circuit

Info

Publication number
JPS6461124A
JPS6461124A JP21774187A JP21774187A JPS6461124A JP S6461124 A JPS6461124 A JP S6461124A JP 21774187 A JP21774187 A JP 21774187A JP 21774187 A JP21774187 A JP 21774187A JP S6461124 A JPS6461124 A JP S6461124A
Authority
JP
Japan
Prior art keywords
frame
circuit
generation polynomial
bit
information bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21774187A
Other languages
Japanese (ja)
Inventor
Hideo Fukuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21774187A priority Critical patent/JPS6461124A/en
Publication of JPS6461124A publication Critical patent/JPS6461124A/en
Pending legal-status Critical Current

Links

Landscapes

  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To simplify circuit constitution by dividing a PCM signal by a generation polynomial without separating an information bit and a check bit in the PCM signal and deciding directly the presence of a transmission bit error by the result. CONSTITUTION:When a sequence converting circuit 3 is added with a frame of an odd number in a received PCM signal 1, the result is added to a frame information bit to a generation polynomial dividing circuit 4, stores a CRC check bit of the frame to a memory provided in the inside tentatively in receiving an even order number frame, the information bit of the frame of number #7(#15) is outputted and the CRC check bit stored in the memory is outputted. The generation polynomial dividing circuit 4 divides by information bit and the CRC check bit by the same generation polynomial as that at the sender side and supplies the residue to a transmission error deciding circuit 5, which decides it if the residue supplied from the generation polynomial division circuit 4 is zero as the absence of transmission error and decides it as the presence of transmission error if the residue exists.
JP21774187A 1987-08-31 1987-08-31 Crc circuit Pending JPS6461124A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21774187A JPS6461124A (en) 1987-08-31 1987-08-31 Crc circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21774187A JPS6461124A (en) 1987-08-31 1987-08-31 Crc circuit

Publications (1)

Publication Number Publication Date
JPS6461124A true JPS6461124A (en) 1989-03-08

Family

ID=16709027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21774187A Pending JPS6461124A (en) 1987-08-31 1987-08-31 Crc circuit

Country Status (1)

Country Link
JP (1) JPS6461124A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0631703A1 (en) * 1992-12-29 1995-01-04 Codex Corporation Efficient crc remainder coefficient generation and checking device and method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4852414A (en) * 1971-11-05 1973-07-23

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4852414A (en) * 1971-11-05 1973-07-23

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0631703A1 (en) * 1992-12-29 1995-01-04 Codex Corporation Efficient crc remainder coefficient generation and checking device and method

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