JPS6455489U - - Google Patents

Description

[Brief explanation of the drawing]

The drawing is a circuit diagram of an alarm clock according to an embodiment of the present invention. 16...Alarm circuit, 26...Sleep time counter, 36...Total sleep time counter, 40...
Operation count counter, 42...Shift register, 4
6...Shift pulse circuit, 54...Subtraction circuit, 5
8...Volume control circuit.

Claims (1)

[Claims for Utility Model Registration] An oscillator circuit, a frequency divider circuit that divides the frequency of a signal from the oscillation circuit, a time display section that displays the time based on the frequency-divided output signal from the frequency divider circuit, and an alarm set. an alarm switch for setting non-setting;
An alarm circuit outputs an alarm notification signal when the time displayed on the time display reaches a preset time when the alarm switch is in the set state, and an alarm circuit outputs an alarm notification signal from the alarm circuit. and a sound generation circuit that generates a sound, the time from when the alarm switch is operated to a set state to when it is operated to a non-operated state is counted using a divided output signal from the frequency dividing circuit. a sleep time counter, and a ^count of the number of times the alarm switch is operated from a set state to a non-set state.
= 1, 2, ...) decimal operation number counter, and starts counting the frequency division output signal from the frequency dividing circuit from the time the alarm switch is operated to the set state, and carries up the operation number counter. a total sleep time counter that clears its count value each time a signal is generated; a shift register in which the count value of the total sleep time counter is preset in response to a carry signal of the operation number counter; and a digit of the operation number counter. a shift pulse generation circuit that outputs a pulse signal for shifting the count value to the lower n bits, which is preset in the shift register in response to the generation of a rising signal; an initial clear circuit that outputs a clear pulse signal when the power is turned on; an initial value setting circuit that presets a preset value in the shift register in response to a pulse signal from a clear circuit; and an initial value setting circuit that compares the count value of the sleep time counter and the count value of the shift register and outputs the difference. 1. A timepiece with an alarm, comprising: a subtraction circuit for increasing or decreasing the alarm volume from the sound generation circuit in response to a difference signal from the subtraction circuit;