JPS6453637A - Digital agc circuit - Google Patents
Digital agc circuitInfo
- Publication number
- JPS6453637A JPS6453637A JP21098387A JP21098387A JPS6453637A JP S6453637 A JPS6453637 A JP S6453637A JP 21098387 A JP21098387 A JP 21098387A JP 21098387 A JP21098387 A JP 21098387A JP S6453637 A JPS6453637 A JP S6453637A
- Authority
- JP
- Japan
- Prior art keywords
- reading
- average level
- difference
- shifting
- digits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE:To a miniaturize hardware, by calculating the average level of an inputted digital signal, detecting a reading 0, shifting only the difference in the reading 0 specified beforehand and counting it with the numeric value of the same number of digits. CONSTITUTION:The average level of an inputted digital signal is calculated 1 and outputted as a binary number. Reading 0 of an average level is detected by a reading 0 detecting means 2 and the difference in the reading 0 of the average level specified beforehand is detected. By a first shifting means 3, only the difference in the reading 0 of an average level calculating means 1 is shifted. A variable gain generating means 5 obtains the gain for fine adjustment from the output of the shifting means 3. A second shifting means 4 shifts the reading 0 of the input only by the above-mentioned difference, a multiplying means 6 multiplies it with the output of the variable gain generating means 5 and outputs it. Thus, the number of the digits to be handled becomes the same and the hardware can be miniaturized.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21098387A JPS6453637A (en) | 1987-08-24 | 1987-08-24 | Digital agc circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21098387A JPS6453637A (en) | 1987-08-24 | 1987-08-24 | Digital agc circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6453637A true JPS6453637A (en) | 1989-03-01 |
JPH0531327B2 JPH0531327B2 (en) | 1993-05-12 |
Family
ID=16598366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21098387A Granted JPS6453637A (en) | 1987-08-24 | 1987-08-24 | Digital agc circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6453637A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0373618A (en) * | 1989-08-14 | 1991-03-28 | Nec Corp | A/d converter |
JP2002246860A (en) * | 2001-02-22 | 2002-08-30 | Kddi Research & Development Laboratories Inc | Device for automatically adjusting amplification level of receiver |
WO2010082488A1 (en) | 2009-01-16 | 2010-07-22 | 株式会社カネカ | Curable composition and cured object formed therefrom |
WO2011089878A1 (en) | 2010-01-19 | 2011-07-28 | 株式会社カネカ | Curable composition |
-
1987
- 1987-08-24 JP JP21098387A patent/JPS6453637A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0373618A (en) * | 1989-08-14 | 1991-03-28 | Nec Corp | A/d converter |
JP2002246860A (en) * | 2001-02-22 | 2002-08-30 | Kddi Research & Development Laboratories Inc | Device for automatically adjusting amplification level of receiver |
WO2010082488A1 (en) | 2009-01-16 | 2010-07-22 | 株式会社カネカ | Curable composition and cured object formed therefrom |
WO2011089878A1 (en) | 2010-01-19 | 2011-07-28 | 株式会社カネカ | Curable composition |
Also Published As
Publication number | Publication date |
---|---|
JPH0531327B2 (en) | 1993-05-12 |
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