JPS6452320U - - Google Patents
Info
- Publication number
- JPS6452320U JPS6452320U JP14760387U JP14760387U JPS6452320U JP S6452320 U JPS6452320 U JP S6452320U JP 14760387 U JP14760387 U JP 14760387U JP 14760387 U JP14760387 U JP 14760387U JP S6452320 U JPS6452320 U JP S6452320U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- dividing
- frequency divider
- frequency
- blocks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Tests Of Electronic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14760387U JPS6452320U (enExample) | 1987-09-29 | 1987-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14760387U JPS6452320U (enExample) | 1987-09-29 | 1987-09-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6452320U true JPS6452320U (enExample) | 1989-03-31 |
Family
ID=31418159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14760387U Pending JPS6452320U (enExample) | 1987-09-29 | 1987-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6452320U (enExample) |
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1987
- 1987-09-29 JP JP14760387U patent/JPS6452320U/ja active Pending