JPS6451533A - System for interrupting data processing system - Google Patents

System for interrupting data processing system

Info

Publication number
JPS6451533A
JPS6451533A JP20809387A JP20809387A JPS6451533A JP S6451533 A JPS6451533 A JP S6451533A JP 20809387 A JP20809387 A JP 20809387A JP 20809387 A JP20809387 A JP 20809387A JP S6451533 A JPS6451533 A JP S6451533A
Authority
JP
Japan
Prior art keywords
interruption
modules
factors
phm1
phmn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20809387A
Other languages
Japanese (ja)
Inventor
Kenji Miyazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP20809387A priority Critical patent/JPS6451533A/en
Publication of JPS6451533A publication Critical patent/JPS6451533A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To attain reduction in the size of a chip by setting interruption request signals to one at every module, outputting bits showing the kind of modules on an internal bus as the high-order part of an interruption vector and outputting bits showing the kind of interruption factors in a self inner part as the low-order part of the interruption vector. CONSTITUTION:When there are interruption requests from respective modules in accordance with peripheral modules PHM1 and PHM2-PHMn, all of which are integrated in the chip, an interruption controller IRC generates the high- order part of the vector to be jumped and outputs it on the address bus BUS. On the other hand, the peripheral modules PHM1-PHMn which have been integrated in the chip respectively have the output terminals of the interruption request signals and they have the interruption factors in a register or the like in the modules. When the interruption factors occur, the peripheral modules PHM1-PHMn output the interruption request signals REQ, receive allowance signals ACK from the interruption controller IRC and output the bits showing the kind of the interruption factors which the register or the like have on the address bus BUS.
JP20809387A 1987-08-24 1987-08-24 System for interrupting data processing system Pending JPS6451533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20809387A JPS6451533A (en) 1987-08-24 1987-08-24 System for interrupting data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20809387A JPS6451533A (en) 1987-08-24 1987-08-24 System for interrupting data processing system

Publications (1)

Publication Number Publication Date
JPS6451533A true JPS6451533A (en) 1989-02-27

Family

ID=16550522

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20809387A Pending JPS6451533A (en) 1987-08-24 1987-08-24 System for interrupting data processing system

Country Status (1)

Country Link
JP (1) JPS6451533A (en)

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