JPS6450330A - Switch - Google Patents

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Publication number
JPS6450330A
JPS6450330A JP20770787A JP20770787A JPS6450330A JP S6450330 A JPS6450330 A JP S6450330A JP 20770787 A JP20770787 A JP 20770787A JP 20770787 A JP20770787 A JP 20770787A JP S6450330 A JPS6450330 A JP S6450330A
Authority
JP
Japan
Prior art keywords
reset
signal
flop
flip
failure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20770787A
Other languages
Japanese (ja)
Other versions
JPH0797461B2 (en
Inventor
Keisuke Konishi
Kenji Shinohara
Norio Iwakiri
Tomofumi Kurashige
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP20770787A priority Critical patent/JPH0797461B2/en
Priority to US07/228,063 priority patent/US4992777A/en
Priority to DE3827161A priority patent/DE3827161A1/en
Publication of JPS6450330A publication Critical patent/JPS6450330A/en
Priority to US07/574,083 priority patent/US5015996A/en
Publication of JPH0797461B2 publication Critical patent/JPH0797461B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Keying Circuit Devices (AREA)

Abstract

PURPOSE:To prevent machines and devices from malfunctioning by reducing a reset load applied on an action body side between reset timings of two switches, outputting a reset failure signal when a reset time exceed a specified value, and issuing a warning. CONSTITUTION:Closedown of an on-off signal S2 is delayed and, from a timer circuit 105 which is caused to start by a closedown detection signal S5 from a 1st input circuit 103, a time-up signal S7 (a reset failure signal) is outputted respectively to a 1st D flip-flop 106a and a 3rd D flip-flop 106c. The output of the 3rd D flip-flop 106c becomes of a high level which is outputted from a failure prediction circuit 106 as a failure prediction signal S13 while other LED (warning means) 40 is lit. A stop or delay in the process of a reset action of an action body is securely caused by the reduction in the reset load of a tapered surface at a flat part of a rotary rod.
JP20770787A 1987-08-10 1987-08-20 Switch Expired - Fee Related JPH0797461B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP20770787A JPH0797461B2 (en) 1987-08-20 1987-08-20 Switch
US07/228,063 US4992777A (en) 1987-08-10 1988-08-04 Switch device with a trouble detecting and indicating function
DE3827161A DE3827161A1 (en) 1987-08-10 1988-08-10 SWITCH DEVICE
US07/574,083 US5015996A (en) 1987-08-10 1990-08-29 Switch device with a trouble detecting and indicating function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20770787A JPH0797461B2 (en) 1987-08-20 1987-08-20 Switch

Publications (2)

Publication Number Publication Date
JPS6450330A true JPS6450330A (en) 1989-02-27
JPH0797461B2 JPH0797461B2 (en) 1995-10-18

Family

ID=16544232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20770787A Expired - Fee Related JPH0797461B2 (en) 1987-08-10 1987-08-20 Switch

Country Status (1)

Country Link
JP (1) JPH0797461B2 (en)

Also Published As

Publication number Publication date
JPH0797461B2 (en) 1995-10-18

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees