JPS5644902A - Triple signal selecting circuit - Google Patents

Triple signal selecting circuit

Info

Publication number
JPS5644902A
JPS5644902A JP12008279A JP12008279A JPS5644902A JP S5644902 A JPS5644902 A JP S5644902A JP 12008279 A JP12008279 A JP 12008279A JP 12008279 A JP12008279 A JP 12008279A JP S5644902 A JPS5644902 A JP S5644902A
Authority
JP
Japan
Prior art keywords
output
input signals
adder
fault signal
fault
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12008279A
Other languages
Japanese (ja)
Inventor
Masaya Ichikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Heavy Industries Ltd
Original Assignee
Mitsubishi Heavy Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Heavy Industries Ltd filed Critical Mitsubishi Heavy Industries Ltd
Priority to JP12008279A priority Critical patent/JPS5644902A/en
Publication of JPS5644902A publication Critical patent/JPS5644902A/en
Pending legal-status Critical Current

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  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE: To eliminate the zero output generated for fault signal disconnection, by applying a false input signal besides the three input signals after fault signal disconnection.
CONSTITUTION: When three input signals I1WI3 are normal, fault signal disconnection switches 2B1W2B3 are connected to the contact (a) side, and switch 6 for false input supply is opend. Input signals I1WI3 are applied to subtractors 41W43 together with output signal ϕ and are sent to adder 3 through limiters 11W13. Limiters output the positive or negative saturation value when their inputs exceed a prescribed range, and output ϕ of adder 3 becomes the intermediate value. When a fault is detected in one of input signals I1WI3, one of switches 2B1W2B3 corresponding to the fault signal is connected to the (b) side, and switch 6 is connected. At this time, the value of a smaller one of normal input signals is output as output ϕ of the adder.
COPYRIGHT: (C)1981,JPO&Japio
JP12008279A 1979-09-20 1979-09-20 Triple signal selecting circuit Pending JPS5644902A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12008279A JPS5644902A (en) 1979-09-20 1979-09-20 Triple signal selecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12008279A JPS5644902A (en) 1979-09-20 1979-09-20 Triple signal selecting circuit

Publications (1)

Publication Number Publication Date
JPS5644902A true JPS5644902A (en) 1981-04-24

Family

ID=14777450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12008279A Pending JPS5644902A (en) 1979-09-20 1979-09-20 Triple signal selecting circuit

Country Status (1)

Country Link
JP (1) JPS5644902A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0370753A (en) * 1989-07-20 1991-03-26 Warner Lambert Co Polymer-base blend composition containing modified starch
JPH0374446A (en) * 1989-07-18 1991-03-29 Warner Lambert Co Polymer-base blend composition containing modified starch

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0374446A (en) * 1989-07-18 1991-03-29 Warner Lambert Co Polymer-base blend composition containing modified starch
JPH0370753A (en) * 1989-07-20 1991-03-26 Warner Lambert Co Polymer-base blend composition containing modified starch

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