JPS6449318A - Analog switch circuit - Google Patents

Analog switch circuit

Info

Publication number
JPS6449318A
JPS6449318A JP62205030A JP20503087A JPS6449318A JP S6449318 A JPS6449318 A JP S6449318A JP 62205030 A JP62205030 A JP 62205030A JP 20503087 A JP20503087 A JP 20503087A JP S6449318 A JPS6449318 A JP S6449318A
Authority
JP
Japan
Prior art keywords
control
timing
trs
cut
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62205030A
Other languages
Japanese (ja)
Inventor
Masami Tsuchida
Yoshimi Iso
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Pioneer Corp
Original Assignee
Hitachi Ltd
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Pioneer Electronic Corp filed Critical Hitachi Ltd
Priority to JP62205030A priority Critical patent/JPS6449318A/en
Publication of JPS6449318A publication Critical patent/JPS6449318A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To prevent the inversion of a switching sequence of a transistor and to execute an exact switching control by making the timing of cut-off in an npn type transistor and a pnp type transistor for constituting an output circuit different from each other. CONSTITUTION:A timing circuit 5 generates a timing signal for control transistors(TRs) Q3, Q6, TRs Q4, Q5, respectively, by allowing it to have a necessary time difference, at the time of A/D and D/A, based on a sample-hold pulse. The control of ON/OFF of an npn type TR Q1 is executed, based on the control of the TRs Q4, Q5, and the control of ON/OFF of a pnp type TR Q2 is executed by an exclusive cut-off means, respectively, based on the control of the TR Q6. Also, said timing of ON/OFF can be determined in advance by the timing circuit 5. In such a way, from a base voltage of the TRs Q1, Q2 of an output circuit at the time of the sample-hold of A/D and the timing of cut-off, the pnp type TR Q2 is cut off by preceding by about 200ns with respect to the npn type TR Q1.
JP62205030A 1987-08-20 1987-08-20 Analog switch circuit Pending JPS6449318A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62205030A JPS6449318A (en) 1987-08-20 1987-08-20 Analog switch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62205030A JPS6449318A (en) 1987-08-20 1987-08-20 Analog switch circuit

Publications (1)

Publication Number Publication Date
JPS6449318A true JPS6449318A (en) 1989-02-23

Family

ID=16500276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62205030A Pending JPS6449318A (en) 1987-08-20 1987-08-20 Analog switch circuit

Country Status (1)

Country Link
JP (1) JPS6449318A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5065610A (en) * 1990-03-12 1991-11-19 Kabushiki Kaisha Kosmek Clamping apparatus for press brake

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5065610A (en) * 1990-03-12 1991-11-19 Kabushiki Kaisha Kosmek Clamping apparatus for press brake

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