JPS6448934U - - Google Patents
Info
- Publication number
- JPS6448934U JPS6448934U JP14331387U JP14331387U JPS6448934U JP S6448934 U JPS6448934 U JP S6448934U JP 14331387 U JP14331387 U JP 14331387U JP 14331387 U JP14331387 U JP 14331387U JP S6448934 U JPS6448934 U JP S6448934U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- variable
- controlled oscillator
- voltage controlled
- loop filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図はこの考案の一実施例による４逓倍ＰＬ
Ｌの構成図、第２図はこの考案の一実施例の入力
ＣＬＫ周波数、電圧制御発振器の中周周波数と可
変分周器の分周数の一例を示した説明図、第３図
は従来の４逓倍ＰＬＬを示す構成図である。
図中の１は位相比較器、２はループフイルター
入力抵抗、３はループフイルターの帰還抵抗、４
はループフイルターの帰還コンデンサー、５はル
ープフイルターのアンプ、６は電圧制御発振器、
７は分周器、８はループフイルター、９は可変分
周器である。なお、図中、同一符号は同一、又は
相当部分を示す。
Figure 1 shows a four-fold PL according to an embodiment of this invention.
2 is an explanatory diagram showing an example of the input CLK frequency, the medium frequency of the voltage controlled oscillator, and the frequency division number of the variable frequency divider in one embodiment of this invention. FIG. 2 is a configuration diagram showing a quadruple PLL. In the figure, 1 is the phase comparator, 2 is the loop filter input resistance, 3 is the feedback resistance of the loop filter, and 4
is the loop filter feedback capacitor, 5 is the loop filter amplifier, 6 is the voltage controlled oscillator,
7 is a frequency divider, 8 is a loop filter, and 9 is a variable frequency divider. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
数を変えることのできる可変分周器を備えた入力
ＣＬＫ周波数可変４逓倍ＰＬＬ回路。 A variable input CLK frequency quadrupling PLL circuit equipped with a voltage controlled oscillator with a constant center frequency and a variable frequency divider that can easily change the frequency division number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14331387U JPS6448934U (en) | 1987-09-19 | 1987-09-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14331387U JPS6448934U (en) | 1987-09-19 | 1987-09-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6448934U true JPS6448934U (en) | 1989-03-27 |
Family
ID=31410022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14331387U Pending JPS6448934U (en) | 1987-09-19 | 1987-09-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6448934U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008514163A (en) * | 2004-09-22 | 2008-05-01 | ジーシーティー セミコンダクター インコーポレイテッド | Apparatus and method for oscillating broadband frequency |
-
1987
- 1987-09-19 JP JP14331387U patent/JPS6448934U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008514163A (en) * | 2004-09-22 | 2008-05-01 | ジーシーティー セミコンダクター インコーポレイテッド | Apparatus and method for oscillating broadband frequency |
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