JPS6448505A - Fet load amplifier circuit - Google Patents

Fet load amplifier circuit

Info

Publication number
JPS6448505A
JPS6448505A JP20549187A JP20549187A JPS6448505A JP S6448505 A JPS6448505 A JP S6448505A JP 20549187 A JP20549187 A JP 20549187A JP 20549187 A JP20549187 A JP 20549187A JP S6448505 A JPS6448505 A JP S6448505A
Authority
JP
Japan
Prior art keywords
load
amplifier circuit
fetj3
resistor
operating point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20549187A
Other languages
Japanese (ja)
Inventor
Toshiro Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20549187A priority Critical patent/JPS6448505A/en
Publication of JPS6448505A publication Critical patent/JPS6448505A/en
Pending legal-status Critical Current

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  • Microwave Amplifiers (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To control the gain of a low frequency side of a band through the proper selection of a resistor by connecting a resistor to a gate of a load FET so as to stabilizing the operating point of the operating FET. CONSTITUTION:The input side is matched by a matching circuit 21 and the output is inputted to a 1st stage amplifier circuit 22. The operating point of the operation FETJ1 of the stage is decided by a load resistor RL. Moreover, the signal is amplified by an output stage amplifier circuit 23 and an FETJ3 is used for a load to obtain a higher output than the case with a resistive load. Moreover, resistors R1, R2 are connected to the gate of the load FETJ3. Since the gate potential of the load FETJ3 is fixed, the operating point of the operation FETJ2 is stabilized. Furthermore, the low frequency gain is controlled to some degree without using a DC cut-off capacitor feedback.
JP20549187A 1987-08-18 1987-08-18 Fet load amplifier circuit Pending JPS6448505A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20549187A JPS6448505A (en) 1987-08-18 1987-08-18 Fet load amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20549187A JPS6448505A (en) 1987-08-18 1987-08-18 Fet load amplifier circuit

Publications (1)

Publication Number Publication Date
JPS6448505A true JPS6448505A (en) 1989-02-23

Family

ID=16507735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20549187A Pending JPS6448505A (en) 1987-08-18 1987-08-18 Fet load amplifier circuit

Country Status (1)

Country Link
JP (1) JPS6448505A (en)

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