JPS6448027U - - Google Patents

Info

Publication number
JPS6448027U
JPS6448027U JP1987143418U JP14341887U JPS6448027U JP S6448027 U JPS6448027 U JP S6448027U JP 1987143418 U JP1987143418 U JP 1987143418U JP 14341887 U JP14341887 U JP 14341887U JP S6448027 U JPS6448027 U JP S6448027U
Authority
JP
Japan
Prior art keywords
back electrode
metal plate
semiconductor device
fixed
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987143418U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987143418U priority Critical patent/JPS6448027U/ja
Publication of JPS6448027U publication Critical patent/JPS6448027U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10157Shape being other than a cuboid at the active surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10158Shape being other than a cuboid at the passive surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Thyristors (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示す縦断面図、第2
図は従来の半導体装置を示す縦断面図である。 1……サイリスタペレツト、6……表面電極、
8……裏面電極、11,11′……金属板、12
……主基板。
Fig. 1 is a vertical sectional view showing an embodiment of the present invention;
The figure is a vertical cross-sectional view showing a conventional semiconductor device. 1... Thyristor pellet, 6... Surface electrode,
8... Back electrode, 11, 11'... Metal plate, 12
...Main board.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体素子の一方の主面に表面電極を他方の主
面に裏面電極を夫々設け、上記裏面電極と主基板
とを金属板を介して固着してなる半導体装置にお
いて、上記金属板の固着面を上記裏面電極の固着
面と同等か若しくはそれより小さく形成したこと
を特徴とする半導体装置。
In a semiconductor device in which a front electrode is provided on one main surface of a semiconductor element and a back electrode is provided on the other main surface, and the back electrode and the main substrate are fixed to each other via a metal plate, the fixed surface of the metal plate is A semiconductor device characterized in that the size is equal to or smaller than the fixed surface of the back electrode.
JP1987143418U 1987-09-18 1987-09-18 Pending JPS6448027U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987143418U JPS6448027U (en) 1987-09-18 1987-09-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987143418U JPS6448027U (en) 1987-09-18 1987-09-18

Publications (1)

Publication Number Publication Date
JPS6448027U true JPS6448027U (en) 1989-03-24

Family

ID=31410226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987143418U Pending JPS6448027U (en) 1987-09-18 1987-09-18

Country Status (1)

Country Link
JP (1) JPS6448027U (en)

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