JPS6447112A - Noise reducer - Google Patents

Noise reducer

Info

Publication number
JPS6447112A
JPS6447112A JP20341187A JP20341187A JPS6447112A JP S6447112 A JPS6447112 A JP S6447112A JP 20341187 A JP20341187 A JP 20341187A JP 20341187 A JP20341187 A JP 20341187A JP S6447112 A JPS6447112 A JP S6447112A
Authority
JP
Japan
Prior art keywords
circuit
signal
low frequency
picture
fed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20341187A
Other languages
Japanese (ja)
Inventor
Hiroyasu Otsubo
Michio Masuda
Hideo Nishijima
Makoto Shiomi
Hitoaki Owashi
Akishi Mitsube
Koichi Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP20341187A priority Critical patent/JPS6447112A/en
Publication of JPS6447112A publication Critical patent/JPS6447112A/en
Pending legal-status Critical Current

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  • Picture Signal Circuits (AREA)

Abstract

PURPOSE:To reduce the noise in a picture signal with a broad band without picture quality deterioration by adding a low frequency picture signal whose noise is reduced by a 1st arithmetic circuit and a delay circuit to a high frequency picture signal by a 2nd arithmetic circuit so as to use a memory of a low capacity. CONSTITUTION:The low frequency component of an input picture signal is separated by an LPF 8 and fed to the 1st and 2nd arithmetic circuits 2, 1. The low frequency signal is multiplied by [1-K] at a coefficient, multiplication circuit 9 and the result is fed to a delay circuit 5. A control circuit 13 stores the signal into a memory 12, reads a signal before a prescribed time and the signal is multiplied by K at a coefficient multiplication circuit 11 and the result is fed to an adder circuit 10. The circuit 10 adds two signals and gives a low frequency signal whose noise is reduced to the circuit 1. An adder circuit 3 gives an added signal between the high frequency signal fed from a subtracter circuit 7 and the low frequency signal whose noise is reduced as the sum signal. Thus, the increase in the memory capacity is suppressed, the deterioration in the picture is avoided and efficient noise reduction is attained.
JP20341187A 1987-08-18 1987-08-18 Noise reducer Pending JPS6447112A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20341187A JPS6447112A (en) 1987-08-18 1987-08-18 Noise reducer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20341187A JPS6447112A (en) 1987-08-18 1987-08-18 Noise reducer

Publications (1)

Publication Number Publication Date
JPS6447112A true JPS6447112A (en) 1989-02-21

Family

ID=16473625

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20341187A Pending JPS6447112A (en) 1987-08-18 1987-08-18 Noise reducer

Country Status (1)

Country Link
JP (1) JPS6447112A (en)

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