JPS6447070A - Manufacture of transistor with broad band gap emitter - Google Patents

Manufacture of transistor with broad band gap emitter

Info

Publication number
JPS6447070A
JPS6447070A JP20459987A JP20459987A JPS6447070A JP S6447070 A JPS6447070 A JP S6447070A JP 20459987 A JP20459987 A JP 20459987A JP 20459987 A JP20459987 A JP 20459987A JP S6447070 A JPS6447070 A JP S6447070A
Authority
JP
Japan
Prior art keywords
layer
band gap
emitter
broad band
sic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20459987A
Other languages
Japanese (ja)
Inventor
Hiroshi Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20459987A priority Critical patent/JPS6447070A/en
Publication of JPS6447070A publication Critical patent/JPS6447070A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To make an allowance for the positional deviation of an emitter in a base region be dispensed with, whereby the base region is made to be able to decrease in area by a method wherein a patterning is performed onto a laminated layer which consists of an n-type SiC layer and a mask layer formed on a substrate so as to mask an element forming region for the formatrion of an element isolating layer and then the peripheral section of the SiC layer is subjected to a selective etching to recede. CONSTITUTION:An epitaxial layer 3, a SiC layer 5 with a broad band gap, and a Si3N4 layer 6 which are to constitute a broad band gap emitter are successively formed on a substrate 1 where an n-type epitaxial layer 3 and a p-type diffusion layer 4 to constitute a base region are formed. The Si3N4 layer 6 and the SiC layer 5 are selectively removed and an element isolating layer 7 is formed on the peripheral section of an element forming region through the layers left unremoved as a mask, and then the peripheral section of the SiC layer 5 is subjected to selective etching to make it recede so as to form a broad band gap emitter 5a and the diffusion layer 4 is made to be exposed around the emitter 5a for the formation of a base contact region, thereafter a conductive layer 81 extending over the element isolating layer 7 is provided to form a base region lead-out wiring.
JP20459987A 1987-08-18 1987-08-18 Manufacture of transistor with broad band gap emitter Pending JPS6447070A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20459987A JPS6447070A (en) 1987-08-18 1987-08-18 Manufacture of transistor with broad band gap emitter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20459987A JPS6447070A (en) 1987-08-18 1987-08-18 Manufacture of transistor with broad band gap emitter

Publications (1)

Publication Number Publication Date
JPS6447070A true JPS6447070A (en) 1989-02-21

Family

ID=16493129

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20459987A Pending JPS6447070A (en) 1987-08-18 1987-08-18 Manufacture of transistor with broad band gap emitter

Country Status (1)

Country Link
JP (1) JPS6447070A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5096844A (en) * 1988-08-25 1992-03-17 Licentia Patent-Verwaltungs-Gmbh Method for manufacturing bipolar transistor by selective epitaxial growth of base and emitter layers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5096844A (en) * 1988-08-25 1992-03-17 Licentia Patent-Verwaltungs-Gmbh Method for manufacturing bipolar transistor by selective epitaxial growth of base and emitter layers

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