JPS6444642A - Data gathering system - Google Patents

Data gathering system

Info

Publication number
JPS6444642A
JPS6444642A JP20219787A JP20219787A JPS6444642A JP S6444642 A JPS6444642 A JP S6444642A JP 20219787 A JP20219787 A JP 20219787A JP 20219787 A JP20219787 A JP 20219787A JP S6444642 A JPS6444642 A JP S6444642A
Authority
JP
Japan
Prior art keywords
clock pulse
data
gathered
clock
reception parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20219787A
Other languages
Japanese (ja)
Inventor
Nagahiko Namikado
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20219787A priority Critical patent/JPS6444642A/en
Publication of JPS6444642A publication Critical patent/JPS6444642A/en
Pending legal-status Critical Current

Links

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  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To connect the same number of signal lines to gather data independently of the quantity of data reception parts by divisionally assigning the clock pulse train from a transmission part to respective reception parts and controlling the level value of a prescribed bit of this clock pulse in accordance with gathered input data. CONSTITUTION:A transmission part 101 is provided with a clock generating circuit 103 which sends a clock pulse 120, a frequency converting circuit 104 which receives the clock pulse 120 to change of the clock frequency, and a comparing circuit 105 which compares an output signal 124 of the frequency converting circuit 104 and a data gathering signal 123. When the clock pulse 120 or data gathering signals 121 and 122 are received, frequencies of the clock pulse in time zones determined in reception parts 102, 110, and 111 are converted to preliminarily determined frequencies and a prescribed bit of the clock pulse is inhibited in accordance with gathered data input to gather data. Consequently, data in reception parts is gathered by one transmission signal line and one reception signal line.
JP20219787A 1987-08-12 1987-08-12 Data gathering system Pending JPS6444642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20219787A JPS6444642A (en) 1987-08-12 1987-08-12 Data gathering system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20219787A JPS6444642A (en) 1987-08-12 1987-08-12 Data gathering system

Publications (1)

Publication Number Publication Date
JPS6444642A true JPS6444642A (en) 1989-02-17

Family

ID=16453575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20219787A Pending JPS6444642A (en) 1987-08-12 1987-08-12 Data gathering system

Country Status (1)

Country Link
JP (1) JPS6444642A (en)

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