JPS6444530A - Digital integrating device - Google Patents

Abstract

PURPOSE:To reduce an error due to leaked current from a capacitor in an analog integrator by providing the titled device two analog integrators and executing the integrating processing of a signal to be integrated and resetting operation alternately in each sampling. CONSTITUTION:When the 1st sampling pulse is inputted to a clock pulse input terminal 20, the analog integrators 2-1, 2-2 respectively execute integrating operation and resetting operation by outputs Q, the inverse of -Q, from a TFF 18. At the time of inputting the 2nd pulse, the output, the inverse of -Q, of an RSFF 19 is turned on, an input switch 9 in a sample & hold circuit 10 is opened, a signal is held, and an analog digital converter 11 executes conversion processing. After ending the processing, the RSFF 19 is reset and the circuit 10 starts the input of the signal again. An integrator 13 integrates an integrated value obtained by the analog integrator 2-2 at the current sampling period to the integrated value obtained up to the preceding times. In the 2nd sampling, the integrating operation is alternated.