JPS6444146A - Data circuit test system - Google Patents

Data circuit test system

Info

Publication number
JPS6444146A
JPS6444146A JP62201119A JP20111987A JPS6444146A JP S6444146 A JPS6444146 A JP S6444146A JP 62201119 A JP62201119 A JP 62201119A JP 20111987 A JP20111987 A JP 20111987A JP S6444146 A JPS6444146 A JP S6444146A
Authority
JP
Japan
Prior art keywords
equipment
data
test
test equipment
bit error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62201119A
Other languages
Japanese (ja)
Inventor
Masahito Fujioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62201119A priority Critical patent/JPS6444146A/en
Publication of JPS6444146A publication Critical patent/JPS6444146A/en
Pending legal-status Critical Current

Links

Landscapes

  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To attain bit error test easily from optional data terminal equipment by providing a data circuit simple test equipment controlled equally as a digital subscriber circuit equipment to an exchange and providing a test pattern generating circuit to the test equipment. CONSTITUTION:For example, a data terminal equipment 51 dials a subscriber number given to the data circuit simple test equipment 4 to be connected to the test equipment. Through the connection, the test equipment 4 sends a bit error test pattern data and detects the test pattern data reflected by a data terminal interface device 11 (set to the loopback mode upon the connection to the test equipment 4), compares it with the sent data to detect and measure the bit error. The result of measurement is sent to the data terminal equipment 51 from the test equipment 4 as a message when the loopback mode of the interface device 11 is released.
JP62201119A 1987-08-12 1987-08-12 Data circuit test system Pending JPS6444146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62201119A JPS6444146A (en) 1987-08-12 1987-08-12 Data circuit test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62201119A JPS6444146A (en) 1987-08-12 1987-08-12 Data circuit test system

Publications (1)

Publication Number Publication Date
JPS6444146A true JPS6444146A (en) 1989-02-16

Family

ID=16435721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62201119A Pending JPS6444146A (en) 1987-08-12 1987-08-12 Data circuit test system

Country Status (1)

Country Link
JP (1) JPS6444146A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4000932A1 (en) * 1989-03-07 1990-09-13 Siemens Ag Altering bit error rate - inputs errors or changing connections to prevent system abuse

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4000932A1 (en) * 1989-03-07 1990-09-13 Siemens Ag Altering bit error rate - inputs errors or changing connections to prevent system abuse

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