JPS6442948A - Clock phase locked loop circuit - Google Patents

Abstract

PURPOSE:To improve the tracking characteristic of input data with respect to a clock by counting the clock number between coincident points of leading of both the clocks, detecting the frequency difference information of both the clocks, increasing/decreasing the number of master clocks and making the phase of the clock of the input data coincident with the phase of the output clock. CONSTITUTION:A frequency difference detection means 1, an adjusting pulse generating means 2, a phase adjusting device 3, and a frequency divider 4 form a digital phase locked loop D-PLL and the D-PL applies loop control till the information T representing the frequency difference between the clocks CK1, CK2 represents zero. Thus, even when the input clock CK1 has any phase error, the period of the output clock CK2 is coincident with the period of the input clock CK1 for each prescribed time and the synchronization is established. Thus, the clock phase synchronizing circuit with excellent tracking is obtained by simple circuit constitution.