JPS6442923A - Analog/digital conversion circuit - Google Patents

Analog/digital conversion circuit

Info

Publication number
JPS6442923A
JPS6442923A JP19954487A JP19954487A JPS6442923A JP S6442923 A JPS6442923 A JP S6442923A JP 19954487 A JP19954487 A JP 19954487A JP 19954487 A JP19954487 A JP 19954487A JP S6442923 A JPS6442923 A JP S6442923A
Authority
JP
Japan
Prior art keywords
circuit
subtraction
voltage generating
voltage
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19954487A
Other languages
Japanese (ja)
Other versions
JP2589318B2 (en
Inventor
Masayuki Ishikawa
Tsuneo Tsukahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP62199544A priority Critical patent/JP2589318B2/en
Publication of JPS6442923A publication Critical patent/JPS6442923A/en
Application granted granted Critical
Publication of JP2589318B2 publication Critical patent/JP2589318B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To contrive the reduction of the power consumption with a simple constitution by giving a specific voltage obtained from a subtraction voltage generating circuit to the 2nd subtraction input terminal of a subtraction circuit composed of an operational amplifier circuit. CONSTITUTION:The subtraction circuit 9 consists of an operational amplifier circuit having a differential amplifier circuit 11 having a gain G (G is a number of >=1) and a voltage being a value of G/(1+G)-fold of a voltage represented by a digital signal D1 obtained from an analog/digital conversion circuit 3 is given to a subtraction input terminal 10B of the subtraction circuit 9 via a subtraction voltage generating circuit 7. Moreover, the subtraction voltage generating circuit 7 consists of a subtraction voltage generating resistance division circuit 31 and a switch circuit 32. Thus, a digital analog conversion circuit being the same as that in a conventional circuit is not required, the constitution is made simple and large power consumption is not needed.
JP62199544A 1987-08-10 1987-08-10 Analog / digital conversion circuit Expired - Fee Related JP2589318B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62199544A JP2589318B2 (en) 1987-08-10 1987-08-10 Analog / digital conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62199544A JP2589318B2 (en) 1987-08-10 1987-08-10 Analog / digital conversion circuit

Publications (2)

Publication Number Publication Date
JPS6442923A true JPS6442923A (en) 1989-02-15
JP2589318B2 JP2589318B2 (en) 1997-03-12

Family

ID=16409592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62199544A Expired - Fee Related JP2589318B2 (en) 1987-08-10 1987-08-10 Analog / digital conversion circuit

Country Status (1)

Country Link
JP (1) JP2589318B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57181226A (en) * 1981-04-30 1982-11-08 Nec Corp Analog-to-digital converter
JPS58206228A (en) * 1982-05-27 1983-12-01 Nippon Denso Co Ltd Analog-digital converter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57181226A (en) * 1981-04-30 1982-11-08 Nec Corp Analog-to-digital converter
JPS58206228A (en) * 1982-05-27 1983-12-01 Nippon Denso Co Ltd Analog-digital converter

Also Published As

Publication number Publication date
JP2589318B2 (en) 1997-03-12

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees