JPS6442745A - Trapping system - Google Patents

Trapping system

Info

Publication number
JPS6442745A
JPS6442745A JP62199107A JP19910787A JPS6442745A JP S6442745 A JPS6442745 A JP S6442745A JP 62199107 A JP62199107 A JP 62199107A JP 19910787 A JP19910787 A JP 19910787A JP S6442745 A JPS6442745 A JP S6442745A
Authority
JP
Japan
Prior art keywords
trap
register
program attribute
address
deciding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62199107A
Other languages
Japanese (ja)
Inventor
Hisashi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62199107A priority Critical patent/JPS6442745A/en
Publication of JPS6442745A publication Critical patent/JPS6442745A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To well-definedly designate an area for setting a trap in a multiple virtual space, and a multi-task environment, by providing a means for deciding simultaneously not only an address but also a program attribute at the time of deciding the trap. CONSTITUTION:The titled system is provided with a memory reference address register 3, an execution program attribute register 4, a trap condition register 5, a trap address register 6, and a trap program attribute register 7. In this state, in accordance with the trap condition register 5, the memory reference address register 3 and the trap address register 6 are compared, and the execution program attribute register 4 and the trap program attribute register 7 are compared. In such a way, at the time of setting a trap, not only an address but also a program attribute are decided simultaneously by a deciding means 8, and in accordance with a result of its decision, the trap is generated, and even in a multiple virtual space and a multi-task environment, the trap can be set well-definedly to an arbitrary area.
JP62199107A 1987-08-11 1987-08-11 Trapping system Pending JPS6442745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62199107A JPS6442745A (en) 1987-08-11 1987-08-11 Trapping system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62199107A JPS6442745A (en) 1987-08-11 1987-08-11 Trapping system

Publications (1)

Publication Number Publication Date
JPS6442745A true JPS6442745A (en) 1989-02-15

Family

ID=16402238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62199107A Pending JPS6442745A (en) 1987-08-11 1987-08-11 Trapping system

Country Status (1)

Country Link
JP (1) JPS6442745A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0195334A (en) * 1987-10-07 1989-04-13 Nec Corp Multi-task address trap system
JPH05241897A (en) * 1992-02-12 1993-09-21 Nec Corp Information processor
JP2005250821A (en) * 2004-03-04 2005-09-15 Renesas Technology Corp Emulator and microprocessor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0195334A (en) * 1987-10-07 1989-04-13 Nec Corp Multi-task address trap system
JPH05241897A (en) * 1992-02-12 1993-09-21 Nec Corp Information processor
JP2005250821A (en) * 2004-03-04 2005-09-15 Renesas Technology Corp Emulator and microprocessor

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