JPS644159B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece that can read out and display a large amount of time information stored in advance at any time.

Conventionally, in electronic watches, time information from bus and train timetables is stored in a storage device such as RAM (random access memory), and when necessary, the above time information is read out and displayed on the display by switching to the time display. It is considered that the By the way, when displaying the time information of a bus or train timetable on a digital display electronic clock, the number of times that can be displayed is limited to two or three at most, so it is not possible to display as much time information as in a timetable. In order to do this, the switching display had to be displayed many times, which was troublesome.

This invention was made in view of the above points,
The purpose is to provide an electronic timepiece that can display a large amount of time information simultaneously.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an overall configuration diagram of an electronic timepiece to which the present invention is applied. In the figure, 11 is an oscillation circuit that outputs a reference frequency signal. The reference frequency signal output from this oscillation circuit 11 is
The frequency is divided into, for example, a 1 Hz signal via the frequency dividing circuit 12 and input to the second counter 13. The second counter 13 counts 1 Hz signals to obtain "second" information. When the second counter 13 counts "60 seconds", it outputs a carry signal to the minute counter 14. The minute counter 14 counts the carry signal to obtain "minute" information. The minute counter 14 sends a carry signal for counting "60 minutes" to the hour counter 1.
Output to 5. The hour counter 15 counts the carry signal to obtain "hour" information. The time information of "hour" and "minute" obtained by the minute counter 14 and the hour counter 15 is sent to the decoder 17 via the OR circuit 16 and displayed on the digital display section 181 in the display section 18. Furthermore, the "minute" information of the minute counter 14 is input to an AND circuit 19, and the "hour" information of the hour counter 15 is input to an AND circuit 20. Then, the "second" information of the second counter 13 is input to the AND circuit 21. When the AND circuit 21 is open, the "second" information is sent to the decoder 22 and displayed on the analog display section 182 in the display section 18 via the OR circuit 23. Further, the switch S is a mode switching switch for switching between the current time display mode and the timetable display mode. The operation signal of this switch S is input to the input terminal T of the T-type flip-flop 24. The signal at the output terminal Q of this flip-flop 24 is input to the one-shot circuit 25, and
The signal is input to the AND circuit 26 as a gate control signal. Further, the signal at the output terminal of the flip-flop 24 is inputted to the AND circuit 21 as a gate control signal. Furthermore, the one-shot pulse output from the one-shot circuit 25 is input to the AND circuits 19 and 20 as a gate control signal, and is also input to the set terminal S of the R-S type flip-flop 27 and the set terminal S of the R-S type flip-flop 28 and 29.
reset terminal R, 60-bit shift register 30
a, 30b and the reset terminal R of the sexagesimal counter 31. Also, the output of the AND circuit 19 is
The output of the AND circuit 20 is 24 to the sexagesimal counter 32.
The signals are respectively input to the advance counter 33. The signal at the output terminal Q of the flip-flop 27 is input as a gate control signal to an AND circuit 34 to which the clock signal φ ₁ outputted from the frequency dividing circuit 12 is applied. The output signal of this AND circuit 34 is input to the sexagesimal counters 31 and 32 and the AND circuit 35, and is also given as a shift signal to the 60-bit shift registers 30a and 30b.
The carry signal output from the sexagesimal counter 32 is input to the set terminal S of the flip-flop 28, the twentyfours counter 33, and the AND circuit 36, respectively. Further, the signal at the output terminal Q of the flip-flop 28 is inputted to AND circuits 35 and 36 as gate control signals, respectively. The output signal of the AND circuit 36 is input to the reset terminal R of the flip-flop 27. On the other hand, the carry signal output from the sexagesimal counter 31 is input to the set terminal S of the flip-flop 29. The signal at the output terminal Q of this flip-flop 29 is output to the AND circuit 37.
and 38 as a gate control signal. Further, the signal at the output terminal of the flip-flop 29 is inputted to the AND circuit 35 and the AND circuit 39 as a gate control signal. 40 is a RAM whose detailed configuration is shown in FIG. this
In the RAM 40, timetables for buses, trains, etc., for example, are preset, and the count value of the 24-decimal counter 33 specifies a row address U, and the count value of the sexagesimal counter 32 specifies a column address L. The contents read from the RAM 40 are input to the 60-bit shift register 30a via the AND circuit 39 and the OR circuit 41. The output of this 60-bit shift register 30a is inputted to the 60-bit shift register 30a via the AND circuit 37 and the OR circuit 41. On the other hand, the output signal of the AND circuit 35 is passed through the OR circuit 42.
It is input to a 60-bit shift register 30b. The output signal of this 60-bit shift register 30b is inputted to the 60-bit shift register 30b via the AND circuit 38 and the OR circuit 42.
The parallel 60-bit data output from the 60-bit shift register 30a is input to an AND circuit 43. Further, parallel 60-bit data output from the 60-bit shift register 30b is input to an AND circuit 44. A 1 Hz signal is inputted to this AND circuit 44 from the frequency dividing circuit 12 as a gate control signal. The data output from the AND circuit 44 is input to the AND circuit 43 via an inverter 45. Furthermore, the output data of the AND circuit 43 is input to the AND circuit 26.
The output data of this AND circuit 26 is transmitted to the analog display section 182 via the OR circuit 23.
is input.

Next, FIG. 2 shows the detailed configuration of the display section 18. In the figure, the display section 18 shows "hour"
It is composed of a digital display 181 that displays "minutes" or "PM" and an analog display section 182 that includes 60 liquid crystal elements arranged in a circumferential manner. Then, the 60 liquid crystal elements display "seconds" or time information preset in the RAM 40.

Next, FIG. 3 shows the configuration of the RAM 40. The RAM 40 has "24×60=1440" sets of memory elements so that it can store 24 hours' worth of information at one-minute intervals. The row address U of the RAM 40 corresponds to "hour" information, and the column address corresponds to "minute" information. The address corresponding to the time information of the timetable in this RAM 40 is “1”
, "0" is written in advance in other addresses.

In this RAM 40, the row address U is specified by the count value of the 24-decimal counter 33, and the column address L is specified by the count value of the sexagesimal counter 32.
A predetermined address of is read. For example, the row address U is "10" and the column address L is "55".
When specified, a “1” signal is output as information set in advance in the 10th row and 55th column of the RAM 40. This shows that trains, buses, etc. will depart at ``10:55''.

Next, the operation of the present invention configured as described above will be explained. First, in FIG. 1, the reference frequency signal output from the oscillation circuit 11 is divided into a 1 Hz signal via the frequency dividing circuit 12, and the second counter 1
3 is input. Then, based on this 1 Hz signal, time information such as "seconds", "minutes", and "hours" are counted by a second counter 13, a minute counter 14, and an hour counter 15. “Minute” of minute counter 14 and hour counter 15
Time information of "hour" is sent to the decoder 17 via the OR circuit 16 and displayed on the digital display section 181. In the normal time display mode, since the output is obtained from the output terminal of the flip-flop 24, the "second" information of the second counter 13 is sent to the decoder via the AND circuit 21 and displayed on the analog display section 182. be done. For example, the current time "10:42:30" is displayed as shown in FIG. 5a.

Then, when switching to the timetable display mode, switch S is operated. By operating the switch S, the output signal of the flip-flop 24 is inverted, an output is obtained from the output terminal, and the AND circuit 21 is closed.
AND circuit 26 is opened. Furthermore, a one-shot pulse is output from the one-shot circuit 25 to reset the flip-flops 28, 29, the 60-bit shift registers 30a, 30b, and the sexagesimal counter 31. Further, the one shot pulse outputted from the one shot pulse circuit 25 is outputted from the AND circuit 1.
9 and 20, and presets the contents of the minute counter 14 and hour counter 15 into the sexagesimal counter 32 and the 24-decimal counter 33. For example, if the current time is
If it is "10:42:30" as shown in figure a, then
The sexagesimal counter 32 has "42", and the 24-decimal counter 3 has "42".
“10” is preset to “3” and “10” respectively. Furthermore, when the flip-flop 27 is set by the one-shot pulse and an output is obtained from the output terminal Q, the gate of the AND circuit 34 is released and the clock signal φ
is given to the sexagesimal counters 32, 31, and the contents are incremented and the 60-bit shift registers 30a, 3
Give a shift signal to 0b. That is, the column address of the RAM 40 is sequentially specified by incrementing the sexagesimal counter 32 and read out from the output terminal of the RAM 40, and the read signal is passed through the AND circuit 37 and the OR circuit 41 in synchronization with the shift signal. Write to 60-bit shift register 30a. and,
When columns ``42'' to ``59'' of row ``10'' that are addressed by the 24-decimal counter 33 of the RAM 40 are read out, the contents of the 60-bit register 30a are as shown in FIG. 4a. The contents of the 10th row and 42nd column to the 59th column of the RAM 40 are stored in the 1st row to the 18th row. Also, at this time, 60-bit shift register 3
Since only a shift signal is applied to 0b, all digits are "0" as shown in FIG. 4a'.
Then, the next clock signal φ is output from the AND circuit 34.
When is output, a carry signal is output from the sexagesimal counter 32. At the falling edge of this carry signal, the flip-flop 28 is set. This results in
AND circuit 35 opens. Here, since the flip-flop 28 is set at the fall of the input carry signal, no signal is output from the AND circuit 36 to the reset terminal R of the flip-flop 27.
Further, the carry signal outputted from the sexagesimal counter 32 is inputted to the 24-digit counter 33, and its count value is incremented by "+1" and set to "11". Therefore, the contents of the 11th row stored in the RAM 40 are sequentially read out by the clock signal φ output from the AND circuit 34, and written to the 60-bit shift register 30a via the AND circuit 39 and the OR circuit 41. At the same time, "1" is sequentially written into the 60-bit shift register 30b in synchronization with the writing into the 60-bit shift register 30a. In this way, from the 11th row 0th column of the RAM 40, the 11th row 41
Time information up to column is 60-bit shift register 3
The contents of the 60-bit shift registers 30a and 30b at that time are as shown in FIG. The contents of the 10th row and 42nd column to the 59th column are stored in the 43rd column to the 60th column, and the 60-bit shift register 30
"1" is stored in the 1st to 42nd digits of b.

In this way, from row 10 and column 42 of RAM 40, 59
When the contents of columns and rows 11 and 0 to 41 are read out, that is, when 60 clock signals φ are output from the AND circuit 34, a carry signal is output from the sexagesimal counter 31, and this carry signal causes the flip-flop to 29 is set. As a result, AND circuits 39 and 35 are closed, and AND circuits 37 and 3
8 opens. Therefore, from now on, the data in the 60-bit shift registers 30a and 30b will be clocked by the clock signal φ.
It circulates through the AND circuit 37 and the OR circuit 41 or the AND circuit 38 and the OR circuit 42 in synchronization with the . When the second carry signal is output from the sexagesimal counter 32, this carry signal is input to the reset terminal R of the flip-flop 27 via the AND circuit 36. As a result, the flip-flop 27 is reset and the AND circuit 34 is reset.
gate closes. Therefore, the clock signal φ
Input to the 60-bit shift registers 30a and 30b is prohibited. The contents of the 60-bit shift registers 30a and 30b at this time are as shown in FIG. 4c and c'. The contents of the 60-bit shift register 30a are sent directly to the AND circuit 43, and the contents of the 60-bit shift register 30b are sent to the AND circuit 44 at 1Hz.
The signal is synchronized with the signal , and is input to the AND circuit 43 via the inverter 45 . As a result, if the current time is "10:42", the time information from 10:42 to 10:59 stored in the RAM 40 will light up as shown in Figure 5b, and from 11:00 to 11:41. The time information up to that point is displayed blinking as shown in FIG.

Note that the present invention can also be applied to analog watches that display pointers optically. in this case,
If the timetable is displayed using the display element that also displays the time, there is no need for a special display element for displaying the timetable.

As detailed above, according to the present invention, multiple pieces of time information such as bus and train timetables within one hour from the current time are displayed simultaneously.
It is possible to provide an electronic timepiece that can reduce the complexity of having to perform switching display many times in order to display a plurality of pieces of time information as in the past.

[Brief explanation of drawings]

The drawings show one embodiment of the invention.
The figure is a block diagram of the entire electronic watch, Figure 2 is a diagram showing the display section of the electronic watch, Figure 3 is a diagram showing the memory contents of the RAM in Figure 1, and Figures 4a to 4c are the figures shown in Figure 1. 60-bit shift register 30 in
A diagram showing changes in the contents of a, a' to c' are the first
FIG. 5A is a diagram showing a change in the contents of the 60-bit shift register 30b, FIG. 5A is a diagram showing a normal time display, and FIG. 11...Oscillation circuit, 18...Display section, 30a,
30b...60-bit shift register, 31, 32
...Sexagesimal counter, 33...Sexagesimal counter, 40
……RAM.

Claims (1)

[Claims] 1. Time measuring means 11, 12, 1 that counts reference signals to obtain current time information in units of hours and minutes.
3, 14, and 15, an analog display device 18 ₂ consisting of 60 display elements arranged in a circumferential manner, and a plurality of storage areas corresponding to times at one-minute intervals. a set time information storage means 40 for storing a plurality of set time information by storing data indicating whether to set the corresponding time in a storage area; and for displaying the set time information on the analog display device ₁₈₂ . a switch S, and when this switch S is operated, hourly unit information and minute unit information of the current time information obtained by the time measuring means 11, 12, 13, 14, 15 are supplied,
One of the plurality of storage areas of the set time information storage means 40 corresponds to a time within one hour from the current time.
Reading means 2 for reading data from 60 storage areas
4, 25, 19, 20, 27-29, 31-3
4, 36 to 37, 39, 41, and the reading means 24, 25, 19, 20, 27 to
29, 31 to 34, 36 to 37, 39, and 41; and a read data storage means 30a for storing the data read out at 29, 31 to 34, 36 to 37, 39, and 41; An electronic timepiece characterized by comprising display control means 43, 26, and 23 for simultaneously displaying minute unit information of set time information within one hour from the current time by simultaneously displaying the same on the device.