JPS5946358B2 - clock device - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic timepiece device having multiple functions. BACKGROUND OF THE INVENTION Electronic timepieces are considered to have a number of functions, such as a calendar, a world clock, and an alarm, in addition to a normal timekeeping function. In this case, a display body corresponding to each function is provided to display the specified function. However, providing a plurality of separate display bodies for displaying functions not only increases the area of the display section but also naturally increases the number of terminals of the LSI, which is not desirable in terms of circuit design. The present invention has been made in view of the above points, and uses a plurality of display bodies used to display timekeeping information to always clearly indicate the currently selected function among the plurality of functions. The object of the present invention is to provide a clock device that can display a clock. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, So, S2. S3 is an operation switch,
Each switch S1. S2. The operation output of S3 is applied to a delayed flip-flop 1.2.3 that operates in synchronization with the timing pulse φe. The outputs of the flip-flops 1 and 2 are connected to the set terminal S of the S-R flip-flop 5 via the AND circuit 4.
The outputs of the flip-flops 2 and 31 are applied to the set terminal S of the S-R flip-flop 7 via the AND circuit 6. Further, the output of the flip-flop 3 is applied to the trigger input terminal T of the trigger flip-flop 8. Therefore, the outputs of the flip-flops 1 and 5 are transmitted to the outputs of the flip-flops 1 and 8 via the AND circuit 9.
The outputs of are respectively applied to the function control circuit 11 via the AND circuit 10. Furthermore, the output of the flip-flop 2 is applied to the set terminal S of the S-R flip-flop 12, and the Q-side output of this flip-flop 12 is applied to the input terminal e of the function control circuit 11 through the AND circuit 13 together with the output of the flip-flop 1.
added to. This function control circuit 11 performs correction control of a timekeeping section, data setting to a memory section, or counting control, which will be described later.
14c and control output terminals 15a to 15c, and the output of the output terminal 15a is applied to the reset terminal R of the flip-flop 5. Further, the signal outputted from the output terminal 15b of the function control circuit 11 is applied to the reset terminal R of the flip-flop 8 via the OR circuit 16 together with the output of the flip-flop 7, and the signal outputted from the output terminal 15c is , are applied to the reset terminal R of the flip-flop 12 via the OR circuit 17 together with the output of the flip-flop 5.7. Further, the reset terminal H of the flip-flop 7 is supplied with the output of a delayed flip-flop 18 that operates in synchronization with the timing pulse φe. The outputs of the flip-flops 1 and 7 are applied to the input terminal of the flip-flop 18 via an AND circuit 19. Therefore, the output terminals 14a to 14 of the function control circuit 11
The signal output from C is applied to one input terminal of AND circuits 20a to 20c, and the other input terminals of AND circuits 20a to 20c are supplied with timing signals W2 to W4 specifying different functional areas within the timekeeping circuit. Given. These timing signals W2 to W4 are signals specifying different functional areas within the timekeeping section, details of which will be described later.
0a is W3, AND circuit 20b is W and circuit 2
W2 is given to 0c. The outputs of the AND circuits 20a to 20c are applied to one input terminal of the adder circuit 23 in the timekeeping section 22 through the OR circuit 21 together with the timing signal 1. The output of the clock shift register 24 is applied to the input terminal a. The adder circuit 23 adds the signals applied to input terminals a and b, and transfers the addition result to a 4-bit shift register 25.
Send to. Further, the carry signal output from the adder circuit 23 is 1
The signal is returned to the input terminal of the adder circuit 23 via the bit delay circuit 26 and the OR circuit 21. Then, the output of the shift register 25 is applied to the input terminal of the shift register 24. This shift register 24 has, for example, a 16-digit configuration as shown in detail in FIG.
6. Furthermore, each digit has a 4-bit configuration, and each bit is designated by timing signals J0 to J4. Further, the shift register 24 is divided into four areas of four digits each, and each area is designated by timing signals W1 to W4. The first area designated by the timing signal W1 includes a frequency dividing section that divides the signal given at the timing of K1 Jo, and a signal with a period of 1 second that is obtained by counting the output of this frequency dividing section. It consists of a forward counter. The second area designated by the timing signal W2 is the normal time section, where the output of K4 digits is sequentially counted to reach ``10''.
6. Performs timekeeping operations in units of seconds, 1 minute, 10 minutes, and hours.
It consists of decimal, decimal, hexadecimal, and decimal counters. The third area designated by the timing signal W3 is the calendar section, which is composed of hexadecimal, decimal, quaternary, and hexadecimal counters that count in units of "7th day,""1stday,""10thday," and "month." It has become. The area specified by the timing signal W4 is a memory section and has functions such as a separate clock, and it sequentially counts the output of K4 digits and performs timekeeping operations in units of "10 seconds,""1minute," and "10 minutes." It consists of hexadecimal, decimal, hexadecimal, and decimal counters. The input signals of the first to third bits 25a to 25c of the shift register 25 are sent to a carry control circuit 27 that performs carry control for each counter in the shift register 24. The output of is applied to the input terminal of the adder circuit 23 via the OR circuit 21. Also, the first to fourth bits 25 of the shift register 25
The outputs of a to 25d are applied to the decoder 28. This decoder 28 is for obtaining a drive signal for the display section, and the signal outputted from its output terminal a is sent to the AND circuit 2.
It is applied to one input terminal of 9a to 29d. The outputs of the AND circuits 29a to 29c are sent via the OR circuit 30 to the time/month/day display section 32 in the display device 31, an example of which is shown in FIG. sent to. This second/day of the week display section 33 has seven display bodies 34□ to 347.
Each of the display bodies 34 to 347 displays a 10 second unit, a day of the week, and morning and afternoon. That is, the display 341 indicates 0 to 9 seconds and Sunday, the display 34□ indicates 010 to 19 seconds and Monday, and the display 343
20-29 seconds and Tuesday, display 344 shows 30 seconds.
The display 345 displays 40-49 seconds and Thursday, the display 346 displays 50-59 seconds and Friday, and the display 34□ displays morning and afternoon divisions and Saturday. Further, the display bodies 341 to 346 display designated functions such as stopwatch ST, counter CU, world clock WT, separate clock OT, alarm AL, and alarm alarms CA and L. In addition, the display body 34. ~346, other specified display,
For example, each country in the world clock, for example Tokyo T K 01
San Francisco SF1 Chicago CGO, New York N
It is possible to display country designations such as YO10, RON, Paris, PAR, etc. In addition, in FIG. 1, the decoder 28 has an input signal

[0]
- Output terminal corresponding to [5]. -b5, each output terminal. The signal output from -b5 is applied to six AND circuits 35 together with an IHz rectangular wave signal and a timing signal 5. The outputs of these AND circuits 35 are displayed on display bodies 341 to 346.
The signals for flushing drive are applied to AND circuits 37a to 37f via OR circuits 36a to 36f, respectively, and the outputs of these AND circuits 37a to 37f provide
Display bodies 34□ to 346 in the seconds/day of the week display section 33 are driven. On the other hand, the outputs of the first to third bits 25a to 25C of the shift register 25 are added to each bit of a 3-bit register 38 and to one input terminal of three AND circuits 39. 5 is added to the timing signal at the other input end of these AND circuits 39, and its output is sent to the 3-bit register 38.
are applied to three EX-OR circuits (exclusive OR circuits) 40 along with each bit output. The output of each EX-OR circuit 40 is applied to an AND circuit 42 via an inverter 41, and the output of this AND circuit 42 is applied to an AND circuit 43 together with an IHz rectangular wave signal. Furthermore, the output of this AND circuit 43 is commonly applied to the input terminals of AND circuits 37a to 37f via an inverter 44. The 3-bit register 38 operates in synchronization with a timing signal given via an AND circuit 49, and each bit output is sent to a decoder 50. This decoder 50 reads the contents of the 3-bit register 38, that is, the contents of the 5th digit read out from the shift register 24;
In other words

Signals are selectively output from six output terminals according to the values [0] to [5], and the output of this decoder 50 is sent to the function control circuit 11 and also to the OR circuits 36a to 36a.
It is applied to AND circuits 37a to 37f via 36f. Further, the output of the AND circuit 51 is given as a gate signal to the AND circuit 49, and the output of the flip-flop 1 is connected to one input terminal of the AND circuit 51.
2, and the output of the flip-flop 18 is applied to the other input terminal. Furthermore, the outputs of the AND circuits 45a to 45d are given as gate signals to the AND circuits 29a to 29d. The AND circuit 45a is a gate that obtains a designated signal for normal time display, and its input terminal receives timing signals of 6+, 7+, and 8, and the outputs of the flip-flops 1 and 5 are sent to the OR circuit 53. and inverter 46
and the outputs of flip-flops 7.8 are applied via inverters 47.48, respectively. The AND circuit 45b is a gate that obtains a designated signal for displaying a calendar, and its input terminal receives a timing signal of 1 for 1o+ and 12 for 10, and the outputs of the OR circuit 53 and the inverters 47 and 48. Given. The AND circuit 45c is a gate that obtains a designation signal for displaying the memory section, and has timing signals 14+, 1, . 16 is given to the input terminal, and the outputs of the flip-flop 8 and the inverters 46 and 47 are given. The AND circuit 4Sd is a gate for obtaining a designated signal for displaying the 7th day of the week (Sunday to Saturday), and its input terminal receives a timing signal of 9 and the outputs of the OR circuit 53 and the inverter 47. Note that the pulse φe given as a timing signal to the delayed flip-flops 1 to 3 and 18 is a signal generated at the final timing, that is, at the timing of 16·J4 every time the shift register 24 makes one round. Next, the present invention configured as described above will be explained in detail. Functions are specified by operating switches 81 to S3 individually or in combination. When switches S to S3 are not operated, the normal time is displayed, but when only switch S1 is operated. displays a calendar type display. Furthermore, if only switch S2 is operated, a time adjustment command is issued, and switch S1. If S2 is operated at the same time, a calendar correction command is issued. After the correction command is issued, the time or calendar is corrected by operating the switch S. Further, when the switch S3 is operated alone, the memory section is displayed. Further, when the switches S2 and S3 are operated simultaneously, the function designation becomes valid, and the next operation of the switch S1 performs the function designation. In this case, the arbitrary function is selected depending on the timing at which the switch S1 is operated. Therefore, when the switches 81 to S3 are not tilted or operated, the outputs of the flip-flops 1 to 3 are 0", and the other flip-flops 5°7.8 are all reset. Therefore, the inverter 46 The output of 48 becomes 1'', the gate of only the AND circuit 45a among the AND circuits 45a to 45d is opened, and the 1'' signal is output from the AND circuit 45a at the timing of K6 to 8. This AND circuit 45a AND circuit 29a by the output of
of the output signal from the output terminal a of the decoder 28, the gate of the normal time part in the shift register 24 is
The signal corresponding to 8 is selected and sent to the time/month/day display section 32 via the OR circuit 30. As a result, the normal time is displayed in the time/month/day display section 32. Also, the output terminal of the decoder 28. The signal output from -b5 is selected by the timing signal 5 in the AND circuit 35 to select the contents of 5 in the register 24, that is, a signal in units of 10 seconds, and the OR circuits 36a to 3
It is applied to AND circuits 37a to 37f via 6f. At this time, the outputs of the inverters 46 and 44, which are given as gate signals to the AND circuits 37a to 37f, are both °°1.
'', therefore, signals are selectively output from the AND circuits 37a to 37f according to the output of the decoder 28 and sent to the seconds/day of the week display section 33. As a result, in the seconds/day of the week display section 33, the display 341 ~3
46 are displayed sequentially in units of 10 seconds. In this case, since the signal applied to the second/day of the week display section 33 is modulated by the IHz signal in the AND circuit 35, one selected display on the second/day of the week display section 33 is flashed for 10 seconds. Incidentally, the shift register 24 always performs a timing operation by dividing the signal applied to the adder circuit 23 via the OR circuit 21 at a timing of 1.Jl using a frequency dividing section. Therefore, when the switch S1 is operated alone while the normal time display is being performed as described above, the display contents are switched from the time display to the calendar display. That is, when the switch S1 is operated, the 11199 signal is read into the flip-flop 1 in synchronization with the timing pulse φe. As a result, the output of flip-flop 1 and the inverter 47
．． The output of 48 becomes 11191, and the AND circuit 45b
, 45d are selected, and from the AND circuit 45b to 1o-
A "1" signal is outputted from the AND circuit 45d at a timing of 1□, and a "1" signal is output from the AND circuit 45d at a timing of 9. The gate of the AND circuit 29b is opened by the signal outputted from the AND circuit 45b at the timing of 1o- and □2, and among the signals outputted from the output terminal a of the decoder 28, the signal in the calendar part of the shift register 24 is 1o-
A signal corresponding to the month/day data of 12 is selected and sent to the time/month/day display section 32 via the OR circuit 30. As a result, the time/month/day display section 32 displays a calendar, that is, a month and a calendar. Further, the gate of the AND circuit 29d is opened by a signal outputted from the AND circuit 45d at the timing of . The signal corresponding to is selected and sent to the second/day of the week display section 33. As a result, in the second/day of the week display section 33, the display bodies 341 to 3
46 displays the day of the week. At this time, since the output of the inverter 46 is I+011, the gates of the AND circuits 37a to 37f are closed, and input of seconds data to the seconds/day of the week display section 33 is prohibited. When you release your hand from the switch S1, its contact opens, and the next timing pulse φe causes the flip-flop 1 to read °'0'' again, returning to the initial time display state. In other words, by operating the switch S1. During this time, the calendar is displayed.Also, when the switch S3 is momentarily operated independently, the contents of the memory section are displayed instead of the normal time.In other words, when the switch S3 is operated, the calendar is synchronized with the timing pulse φe. Then, the "1"' signal is read into the flip-flop 3, and the flip-flop 8 is set. As a result, flip-flop 8 and inverter 46.47
The output of the inverter 48 is 1'', and the output of the inverter 48 is 0°'.
c is selected, and the 'f 1 +1 signal is outputted from the AND circuit 45c at timings 14 to 16. The gate of the AND circuit 29c is opened by the signal output from the AND circuit 45c at timings 14 to 16, and among the signals output from the output terminal a of the decoder 28, the signal output from the memory section of the shift register 24 is A signal corresponding to the contents of 16 is selected and sent to the time/month/day display section 32 via the OR circuit 30. As a result, the contents of the memory section are displayed in the time/month/day display section 32. Then, when the switch S3 is instantaneously operated again, a "1" signal is read into the flip-flop 3 in synchronization with the timing pulse φe, and an n 1 n signal is sent to the trigger flip-flop 8. This flip-flop 8 is inverted by the signal from the flip-flop 3, and the previous output ej
The state of 1tl is reversed to the state of output 91097 -. As a result, everything returns to the initial state and the normal time display is performed again. When the switch S2 is operated alone, a command to adjust the time is generated, and the time is adjusted by the subsequent operation of the switch S1. That is, when the switch S2 is operated, the flip-flop 2 is switched in synchronization with the timing pulse φe. +1 tt times the signal is read and its output becomes °1''. As a result, the flip-flop 12 is set and the H1+1 signal is sent to one input terminal of the AND circuit 13, making it possible to make corrections. In this state Next, when 81 is operated, the timing pulse φe
The ``°1'' signal is read into the flip-flop 1 in synchronization with , and the output signal is sent to the function control circuit 11 via the AND circuit 13. When a signal is applied, first, at a timing of 6.Jl, a "1" signal is output from the output terminal 14c every 2 seconds, for example. The "°1" signal outputted from this output terminal 14c is taken out via an AND circuit 20 gate-controlled by a timing signal W2, and further sent to an adder circuit 23 via an OR circuit 21. As a result, the shift In the normal time section of the register 24, K
A counter of 8, that is, a counter in units of hours, is incremented by 1 every 2 seconds. Therefore, the time is corrected in hours by keeping the switch S1 closed until the hour display matches the correct time, and then opening the switch S1 when the times match. After the above-mentioned time adjustment in "hour" units, when the switch S1 is operated again and a °°1'' signal is applied to the input terminal C of the function control circuit 11, the function control circuit 11 outputs the signal from the output terminal 14c every 2 seconds. The "1" signal is output at the timing of 7.Jl, and the time is adjusted in units of "10 minutes" in the same manner as in the above case. In this way, each time the switch S1 is operated, the time is adjusted in a different unit. After completing the time adjustment, when the switch S1 is operated, a °°1'' signal is output from the output terminal 15c of the function correction circuit 11, and the flip-flop 12 is reset to return to the initial state.Switches S1 and S2 are simultaneously operated. When operated, a calendar correction command is generated, and the calendar correction is performed by the subsequent operation of switch S1. That is, when switches S1 and S2 are operated simultaneously, "1" is output to flip-flops 1 and 2 in synchronization with timing pulse φe. The signal is read and its output becomes "1". As a result, the output of the AND circuit 4 becomes "1" and the flip-flop 5 is set. The output of the above flip-flop 2 is the flip-flop 12
However, since the output of the flip-flop 5 is applied to the reset terminal R of the flip-flop 12, it is held in the reset state. Further, since the output of the flip-flop 5 becomes .degree.1",
d, the AND circuits 45b and 45d are selected, and the display is switched to the calendar display as described above. After that, when only switch S1 is operated, flip-flop 1
A "1" signal is outputted from the flip-flop 5 and is applied to the AND circuit 9 together with the output of the flip-flop 5. Therefore, the AND circuit 9 outputs the ``1'' signal, which is applied to the input terminal a of the function control circuit 11. This function control circuit 11 outputs an output while the ``1'' signal is applied to the input terminal a. A signal °゛1''1'' is sent from the end 14a every 2 seconds at a timing of 1□.Jl. In the same manner, the function control circuit 11 outputs the output terminal 14 every time a "1" signal is applied to the input terminal a in response to the operation of the switch S1.
The timing of the signal output from a changes in the order of 1, .Jl, 1o-Jl, and 9.Jl. The signal outputted from the output terminal 14a of the function control circuit 11 is taken out via an AND circuit 20a gate-controlled by a timing signal W3, and further outputted from an OR circuit 21.
is sent to the adder circuit 23 via. Therefore, the calendar is corrected in accordance with the operation of the switch S1, as in the case of time correction. After the modification is completed, the output terminal 15a of the function control circuit 11 is
'' signal is output, and the flip-flop 5 is reset. When the switches S2 and S3 are operated simultaneously, the function specification becomes valid, and then the shift register 24 is changed according to the operation timing by operating the switch S1. The function to be stored in the memory section is specified. In other words, when switches S2 and S3 are operated simultaneously, the flip-flops 2 and 3 are stored in synchronization with the timing pulse φe.
When the ``1''1'' signal is received, the AND circuit 6 outputs the 11119 signal and the flip-flop 7 is set. Furthermore, the flip-flop 8 is set by the output of the flip-flop 3. By setting the flip-flop 7, the output of the inverter 47 becomes IIO? +, all the gates of the AND circuits 45a to 45d close, and their outputs become 0''. Therefore, the output of the OR circuit 30 becomes O'', and the time/month/day display section 32 displays. is erased. That is, switch S2. If you operate S3 at the same time, the fourth
The state in which the normal time display is displayed as shown in FIG. At this time, the output of the inverter 46 is "■"'. The gates of AND circuits 37a to 37f are open. Therefore, the signal in units of 10 seconds taken out from the decoder 28 via the AND circuit 35 is transmitted to the seconds/day of the week display section 3 via OR circuits 36a to 36f and AND circuits 37a to 37f.
Sent to 3. For this reason . The display device 31 only displays seconds as shown in FIG. 4, indicating that the function designation has become valid. Next, when the seconds display reaches a position corresponding to the desired function, the function is selected by operating switch S1. For example, if the switch S1 is operated when the second display is in the 40 seconds range, as shown in FIG. 4C, that is, when the display 346 is blinking, the alarm mechanism is designated. That is, when the switch S1 is operated, the signal °゛1''1'' is sent to the flip-flop 1 in synchronization with the timing pulse φe, and its output becomes °1''. Therefore, the output of the AND circuit 19 becomes 1'', and the output from the flip-flop 1 becomes 1''. 1” in synchronization with the timing pulse φe in step 18.
The signal is read and one input terminal of the AND circuit 51 receives "1".
'' signal is given. If the switch S1 is opened in this state, the content of the flip-flop 1 becomes 0'' when the next timing pulse φe is given, and the output of the inverter 52 becomes 1''. Therefore, the output of the AND circuit 51 becomes 1", the output of the AND circuit 49 becomes 1" in synchronization with the timing signal 5, and is given to the register 38. The output of the AND circuit 49 causes the 10 second unit in the 5 digits in the shift register 24 to change to 1". information, that is, second information [4] indicating 40 seconds is read out through the register 25,
Set in register 38. Furthermore, when the output of the AND circuit 51 becomes 1'', the flip-flop 7 is reset and the gate of the AND circuit 19 is closed. Therefore, the content of the flip-flop 18 becomes 0 when the next timing pulse φe is applied. '', and the gate of the AND circuit 51 is closed. Furthermore, by sorting the flip-flop 7 by 7, the output of the inverter 47 becomes e+1 tt. As a result, as described above, the contents of the normal time section in the register 24 are read out and sent to the time/month/day display section 32, where they are displayed as shown in FIG. 4C. The contents held in the register 38 are decoded by the decoder 50 and sent to the function control circuit 11, as well as the OR circuits 36a to 36f and the AND circuit 37.
It is sent to the second/day of the week display section 33 via a to 37f. In this case, since the content of the register 38 is [4], the display 345 of the 40 seconds range, which indicates the alarm function, among the displays 341 to 34□ is lit continuously. However, at the time when the function display and the second display overlap, the display 345, for example, in the case of an alarm function designation, becomes a blinking display. That is, at timing K5, the gate of the AND circuit 39 is opened, and the 5-digit contents of the register 24 are read out and added to the EX-OR circuit 40. At this time, if the content read from the register 24 is [4] and matches the content stored in the register 38, the EX OR circuit 40
The outputs of the inverter 41 are all 0'' and the outputs of the inverter 41 are all 1''.
Then, the AND circuit 42 outputs the ``1'' signal. The output of the AND circuit 42 opens the gate of the AND circuit 43, and the AND circuit 43 outputs an IHz signal. The IH2 signal output from this AND circuit 43 is applied to AND circuits 373 to 37f via an inverter 44. As a result, the output of the decoder 50 is the AND circuit 37a to 3.
When output from 7f, it is modulated by an IHz signal,
The display on the seconds/day of the week display section 33 is flashed as shown in FIG. 4C. However, when the seconds display moves to the 50 seconds range, the 6-digit seconds information read out via the AND circuit 39 and the contents of the register 38 no longer match, so the EX-OR circuit 40 is 1" signal is output, and the output power of any of the inverters 41 becomes 0". As a result, the output of the AND circuit 42 becomes 0", the gate of the AND circuit 43 is closed, and the output of the inverter 44 becomes 1".
It becomes Pa. Therefore, the output of the decoder 50 is directly output from the OR circuit 36a to
36f and AND circuits 37a to 37f to the second/day of the week display 33, and a display 345 indicating an alarm function.
is continuously driven for display as shown in FIG. 4a. However, since the seconds information taken out from the decoder 28 via the AND circuit 35 is modulated by the IHz signal as described above, the display 346 indicating the 50 seconds range is not brushed as shown in FIG. 4d. Driven. In this way, by continuous drive and flushing drive,
Function display and seconds display are performed separately. With the function specified as described above, by operating the switch S1, it is possible to set data or perform counting control on the memory section of the register 24. That is, when the switch S1 is operated, the flip-flop 1 receives a signal "1"1", and its output is sent to the AND circuit 10.
It is applied to the input terminal of the function control circuit 11 via the input terminal. The function control circuit 11 performs predetermined function control in accordance with the signal from the decoder 50 when a signal is applied to the input terminal. The function control circuit 11 outputs a signal "°1" from the output terminal 14b to the memory section of the register 24 every 2 seconds at a timing of 16.Jl while a signal is applied to the input terminal. The signal outputted from this output terminal 14b is taken out via an AND circuit 20b gate-controlled by a timing signal w4, and further passed through an OR circuit 21 to an atter circuit 20.
3 and 16 digits in the memory section. Similarly, each time switch S1 is operated, 15.J
A signal with a period of 2 seconds is output to 1, K14 and Jo in the order of 13 and Jl. Therefore, the value of the memory section can be set to a predetermined value by operating the switch S1 every time the content of each digit of the memory section being displayed reaches a desired value. When the switch S1 is operated again after the data has been set, a signal of "1"1" is generated from the output terminal 15b of the function control circuit 11, and the flip-flop 8 is reset. As a result, the display returns to the initial state and the display contents on the display device 31 are switched from the contents of the memory section to the display of the normal time. Even when the display is switched to the normal time display, the display 345 indicating the specified alarm function is lit continuously.
You can always check the functions stored in the memory section. Although not shown, if the set time of the alarm is compared with the normal time and they match, a notification is given by a buzzer or the like. In addition, functions that set numerical values other than alarms, such as world clock WT, separate clock OT, and calendar alarm CAL for long-term months and days, are also stored in the memory section in the same manner as the above alarm function. can be done. On the other hand, in the case of the function of the stopwatch ST1 counter CU, counting control is performed in the memory section by operating the switch S1. Also, when the city name of the world clock WT is displayed, one of the corresponding displays in the second/day of the week display section 33 lights up continuously, and the 10-second display is displayed while flashing. Of course, even in this case, flashing will be performed when both displays overlap on the same display body. In the above embodiment, functions are displayed by continuously driving the display and seconds are displayed by flashing, but other methods may also be used, such as differentiating the flashing period to differentiate the display. Of course, display means may also be used. Furthermore, if the function display and the seconds display overlap, it goes without saying that a frequency such as 0.5 Hz, which is different from the flashing of the seconds display, may be used for the display. Further, in the above embodiment, seconds and functions are displayed in two display modes, but the number of display modes may be further increased to display a plurality of functions at the same time. That is, in the above embodiment, the case where various functions are selectively set in one memory section has been explained, but in the case where a plurality of memory sections are provided and different functions are set in each memory section, or when n(2 When m (>n) functions are selectively set for the above) memory sections, a plurality of functions in use are displayed simultaneously. As described above, according to the present invention, the functions are always displayed together with the timekeeping information in different display modes, so the currently selected function can be easily confirmed at any time, and the display body can also be displayed. Since it is used to display both, there is no need to provide a special display, and the display becomes extremely compact, making it effective for use in small timepiece devices such as wristwatches.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing details of a timekeeping register in the same embodiment, and FIG.
The figure shows the configuration of the display device in the same embodiment, and FIGS. 4a and 4d are diagrams showing the state of display contents for explaining the operation of the same embodiment. 1-3, 5-8, 18...Flip-flop,
24.38...Shift register, 28,50.
... Decoder, 31 ... Display device, 32
・・・・・・Time/month/day display section, 33...seconds/
Day of the week display section, 34□ to 347...Display body.

Claims (1)

[Claims] 1. In a clock device equipped with a clock function that obtains time information by counting reference signals and multiple types of secondary functions other than the clock function, displaying hour and minute information among the time information obtained by the clock function. a plurality of display bodies that sequentially display time information other than the hours and minutes obtained by the clock function; and a designation means for designating one of the plurality of types of secondary functions; switching display means for switching and displaying the information of the secondary function designated by the designation means on the digital display section instead of the hour and minute information; display means for displaying type information of the secondary function designated by the designation means on the plurality of display bodies at the same time as the time and non-separation time information; In order to distinguish between the time information for non-preparation and the type information, the display for displaying the time information for non-preparation and the display for displaying the type information are illuminated in different states. A timepiece device comprising a display control means for displaying information.