JPS6441252A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6441252A
JPS6441252A JP19748187A JP19748187A JPS6441252A JP S6441252 A JPS6441252 A JP S6441252A JP 19748187 A JP19748187 A JP 19748187A JP 19748187 A JP19748187 A JP 19748187A JP S6441252 A JPS6441252 A JP S6441252A
Authority
JP
Japan
Prior art keywords
lead
solder
plated
plating
tin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19748187A
Other languages
Japanese (ja)
Inventor
Kiyoshi Tsuji
Seiichi Nishino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19748187A priority Critical patent/JPS6441252A/en
Publication of JPS6441252A publication Critical patent/JPS6441252A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the forming of compounds between metals, and avoid the formation of solder-bridge between adjacent pins, by performing lead-plating and tin-lead-plating for external leads. CONSTITUTION:On an island, a semiconductor element 3 is fixed, and connected electrically to an internal lead 6' with a fine metal wire 2. Sealing resin 1 is arranged so as to cover them. A U-shaped external leads 6 lead-out from the resin 1 are plated with lead 5, and then plated with tin-lead 4. Since the melting point of the metal 5 is higher than that of the metal 4, surface tension becomes hard to generate at the time of soldering. When the semiconductor is mounted, the solder extends uniformly over the whole part of the leads 6. Thereby, the forming of compound between metals can be prevented, and the formation of solder-bridge between adjacent pins can be avoided.
JP19748187A 1987-08-06 1987-08-06 Semiconductor device Pending JPS6441252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19748187A JPS6441252A (en) 1987-08-06 1987-08-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19748187A JPS6441252A (en) 1987-08-06 1987-08-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6441252A true JPS6441252A (en) 1989-02-13

Family

ID=16375194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19748187A Pending JPS6441252A (en) 1987-08-06 1987-08-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6441252A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6433418B1 (en) 1998-07-24 2002-08-13 Fujitsu Limited Apparatus for a vertically accumulable semiconductor device with external leads secured by a positioning mechanism

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5730353A (en) * 1980-07-30 1982-02-18 Nec Corp Semiconductor device
JPS63187655A (en) * 1987-01-30 1988-08-03 Furukawa Electric Co Ltd:The Lead frame for electronic component

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5730353A (en) * 1980-07-30 1982-02-18 Nec Corp Semiconductor device
JPS63187655A (en) * 1987-01-30 1988-08-03 Furukawa Electric Co Ltd:The Lead frame for electronic component

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6433418B1 (en) 1998-07-24 2002-08-13 Fujitsu Limited Apparatus for a vertically accumulable semiconductor device with external leads secured by a positioning mechanism

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