JPS6440939U - - Google Patents

Info

Publication number
JPS6440939U
JPS6440939U JP1987134509U JP13450987U JPS6440939U JP S6440939 U JPS6440939 U JP S6440939U JP 1987134509 U JP1987134509 U JP 1987134509U JP 13450987 U JP13450987 U JP 13450987U JP S6440939 U JPS6440939 U JP S6440939U
Authority
JP
Japan
Prior art keywords
detection means
output
subtraction
clock signal
input end
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987134509U
Other languages
Japanese (ja)
Other versions
JPH0646114Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987134509U priority Critical patent/JPH0646114Y2/en
Publication of JPS6440939U publication Critical patent/JPS6440939U/ja
Application granted granted Critical
Publication of JPH0646114Y2 publication Critical patent/JPH0646114Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Position Fixing By Use Of Radio Waves (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例のブロツク図。第
２図はこの考案の一実施例の説明を供するタイミ
ング図。 Ａ……ＤＬＬ回路、１および２……相関器、３
および４……検波器、５……減算増幅器、６……
クロツク信号発生器、８……ＰＮ符号発生器、９
……逆拡散器、１１……利得可変増幅器。 FIG. 1 is a block diagram of one embodiment of this invention. FIG. 2 is a timing diagram illustrating one embodiment of the invention. A...DLL circuit, 1 and 2...correlator, 3
and 4...detector, 5...subtraction amplifier, 6...
Clock signal generator, 8...PN code generator, 9
...Despreader, 11...Variable gain amplifier.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第１の相関出力を検波する第１の検波手段と、
第２の相関出力を検波する第２の検波手段と、第
１の検波手段の出力と第２の検波手段の出力とを
減算し、その減算出力でクロツク信号発生器から
の発生クロツク信号の周波数を制御する減算手段
とを備えた遅延ロツクループ回路において、第１
の検波手段と前記減算手段の一方の入力端との間
および第２の検波手段と前記減算手段の他方の入
力端との間に互に相反する利得調整機能を有する
利得可変増幅器を備えたことを特徴とする遅延ロ
ツクループ回路。 a first detection means for detecting the first correlation output;
A second detection means detects the second correlation output, subtracts the output of the first detection means and the output of the second detection means, and uses the subtraction output to determine the frequency of the clock signal generated from the clock signal generator. a delay lock loop circuit comprising subtracting means for controlling a first
A variable gain amplifier having mutually opposing gain adjustment functions is provided between the second detection means and one input end of the subtraction means and between the second detection means and the other input end of the subtraction means. A delay lock loop circuit featuring:
JP1987134509U 1987-09-04 1987-09-04 Delay locked loop circuit Expired - Lifetime JPH0646114Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987134509U JPH0646114Y2 (en) 1987-09-04 1987-09-04 Delay locked loop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987134509U JPH0646114Y2 (en) 1987-09-04 1987-09-04 Delay locked loop circuit

Publications (2)

Publication Number Publication Date
JPS6440939U true JPS6440939U (en) 1989-03-10
JPH0646114Y2 JPH0646114Y2 (en) 1994-11-24

Family

ID=31393329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987134509U Expired - Lifetime JPH0646114Y2 (en) 1987-09-04 1987-09-04 Delay locked loop circuit

Country Status (1)

Country Link
JP (1) JPH0646114Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0425242A (en) * 1990-05-21 1992-01-29 Mitsubishi Electric Corp Delayed locked loop circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0425242A (en) * 1990-05-21 1992-01-29 Mitsubishi Electric Corp Delayed locked loop circuit

Also Published As

Publication number Publication date
JPH0646114Y2 (en) 1994-11-24

Similar Documents

Publication Publication Date Title
JPH0232248U (en)
JPS6440939U (en)
JPS5761309A (en) Video detecting circuit
JPS5364570A (en) Phase comparator
JPH0312569U (en)
JPH0247513U (en)
JPS6399440U (en)
JPH03114080U (en)
JPH03107839U (en)
JPH0441678U (en)
JPS633644U (en)
JPH0373090U (en)
JPH03117787U (en)
JPH03120147U (en)
JPH0299379U (en)
JPH03107840U (en)
JPH0419825U (en)
JPS61176820U (en)
JPH0268533U (en)
JPS58114610U (en) synthetic amplifier
JPS523473A (en) Signal detecting appliance
JPH0286217U (en)
JPH0336290U (en)
JPS6444769U (en)
JPS63102339U (en)