JPH03107839U - - Google Patents
Info
- Publication number
- JPH03107839U JPH03107839U JP1539690U JP1539690U JPH03107839U JP H03107839 U JPH03107839 U JP H03107839U JP 1539690 U JP1539690 U JP 1539690U JP 1539690 U JP1539690 U JP 1539690U JP H03107839 U JPH03107839 U JP H03107839U
- Authority
- JP
- Japan
- Prior art keywords
- pseudo
- clock
- noise code
- signal
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims 1
- 238000001228 spectrum Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Description
第１図は本考案の第一の実施例を示すブロツク
図、第２図は位相差関数特性図、第３図は位相制
御回路構成例を示すブロツク図、第４図は本考案
の第二の実施例を示すブロツク図、第５図は具体
的構成例を示すブロツク図である。
１……擬似雑音発生器、２……相関器、４……
位相制御手段、５，６，１２……クロツク発生器
。
Fig. 1 is a block diagram showing the first embodiment of the present invention, Fig. 2 is a phase difference function characteristic diagram, Fig. 3 is a block diagram showing an example of the configuration of a phase control circuit, and Fig. 4 is a block diagram showing the second embodiment of the present invention. FIG. 5 is a block diagram showing an example of a specific configuration. 1...Pseudo noise generator, 2...Correlator, 4...
Phase control means, 5, 6, 12...clock generator.
Claims (1)
装置で用いられる擬似雑音符号同期回路において
、受信拡散信号と擬似雑音符号との相関をとるた
めの相関器と、前記受信拡散信号に対して所定の
周波数だけ高いクロツク信号を発生するクロツク
発生器と、前記受信拡散信号と前記クロツク信号
の位相を比較し位相差が所定の値を越えるとこの
クロツク信号の位相を１／Ｎクロツク（Ｎは整数
）分だけ遅らせる位相制御手段と、前記クロツク
発生器からのクロツク信号によつて駆動され前記
擬似雑音符号を発生する擬似雑音発生器とを設け
たことを特徴とする擬似雑音符号同期回路。 A pseudo-noise code synchronization circuit used in a receiving device using direct-sequence spread spectrum communication includes a correlator for correlating the received spread signal and the pseudo-noise code, and a correlator that is higher than the received spread signal by a predetermined frequency. A clock generator that generates a clock signal compares the phases of the received spread signal and the clock signal, and if the phase difference exceeds a predetermined value, delays the phase of this clock signal by 1/N clock (N is an integer). A pseudo-noise code synchronization circuit comprising phase control means and a pseudo-noise generator driven by a clock signal from the clock generator to generate the pseudo-noise code.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1539690U JPH03107839U (en) | 1990-02-19 | 1990-02-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1539690U JPH03107839U (en) | 1990-02-19 | 1990-02-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03107839U true JPH03107839U (en) | 1991-11-06 |
Family
ID=31518704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1539690U Pending JPH03107839U (en) | 1990-02-19 | 1990-02-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03107839U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003236663A (en) * | 2002-02-19 | 2003-08-26 | Daihen Corp | Nonconsumable electrode type arc welding equipment |
| JP4739621B2 (en) * | 2001-12-25 | 2011-08-03 | 株式会社ダイヘン | Consumable electrode arc welding equipment |
-
1990
- 1990-02-19 JP JP1539690U patent/JPH03107839U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4739621B2 (en) * | 2001-12-25 | 2011-08-03 | 株式会社ダイヘン | Consumable electrode arc welding equipment |
| JP2003236663A (en) * | 2002-02-19 | 2003-08-26 | Daihen Corp | Nonconsumable electrode type arc welding equipment |
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