JPS6439876A - Synchronizing signal generating circuit - Google Patents
Synchronizing signal generating circuitInfo
- Publication number
- JPS6439876A JPS6439876A JP19675287A JP19675287A JPS6439876A JP S6439876 A JPS6439876 A JP S6439876A JP 19675287 A JP19675287 A JP 19675287A JP 19675287 A JP19675287 A JP 19675287A JP S6439876 A JPS6439876 A JP S6439876A
- Authority
- JP
- Japan
- Prior art keywords
- horizontal
- frequency dividing
- vertical
- signal
- noise
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Synchronizing For Television (AREA)
Abstract
PURPOSE:To obtain horizontal and vertical pulses, which are necessary to the driving of a CCD without receiving the influence of frequency dividing noise by using a frequency dividing circuit to operate only during horizontal and vertical blanking periods. CONSTITUTION:A signal is supplied from an oscillator 1, which generates the frequency signal of the integer-fold of a horizontal synchronizing frequency, to integrated circuits (IC) 1 and 2. The IC1 outputs the synchronizing signals of various types and the synchronizing signals HD and VD of horizontal and vertical scannings with using a horizontal frequency dividing counter 2, a vertical frequency dividing counter 3 and a decoder 4. Though it is highly possible that the frequency dividing noise, which is generated by the horizontal frequency dividing counter 2 of this IC, is mixed, however, the noise can be removed by the simple low-pass filter of a C-R. The IC2 is operated with receiving the signals HD and VD from the IC1. Namely, since the horizontal frequency dividing counter 8 and the decoder 9 are reset by the input rising of the HD signal and the horizontal frequency dividing counter 8 starts operating, a CCD vertical driving pulse and a horizontal blanking signal can be made by decoding this operation.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62196752A JP2856394B2 (en) | 1987-08-05 | 1987-08-05 | Synchronous signal generation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62196752A JP2856394B2 (en) | 1987-08-05 | 1987-08-05 | Synchronous signal generation circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6439876A true JPS6439876A (en) | 1989-02-10 |
JP2856394B2 JP2856394B2 (en) | 1999-02-10 |
Family
ID=16363024
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62196752A Expired - Fee Related JP2856394B2 (en) | 1987-08-05 | 1987-08-05 | Synchronous signal generation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2856394B2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57184373A (en) * | 1982-04-21 | 1982-11-13 | Hitachi Ltd | Pulse generating circuit |
-
1987
- 1987-08-05 JP JP62196752A patent/JP2856394B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57184373A (en) * | 1982-04-21 | 1982-11-13 | Hitachi Ltd | Pulse generating circuit |
Also Published As
Publication number | Publication date |
---|---|
JP2856394B2 (en) | 1999-02-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS57184376A (en) | Signal output circuit of image pickup device | |
TW200614635A (en) | Charge pump circuit | |
JPS57154983A (en) | Multiplying circuit of horizontal scan frequency | |
FR2454734A1 (en) | TELEVISION SYNCHRONIZATION SIGNAL GENERATING DEVICE | |
KR830008597A (en) | Television receiver | |
MY105383A (en) | Display locked timing signals for video processing. | |
JPS6439876A (en) | Synchronizing signal generating circuit | |
ES8707837A1 (en) | Sychronizing the operation of a computing means with a reference frequency signal. | |
CA2077532A1 (en) | Phase control circuit | |
GB2279518A (en) | Method and apparatus for digital modulation using concurrent pulse addition and substraction | |
JPS5752268A (en) | Horizontal synchronizing circuit | |
JPS57199370A (en) | Synchronizing signal resetting circuit of video camera | |
JPS56104577A (en) | Field distinction circuit | |
KR900006305Y1 (en) | Horizontal and vertical synchronizing signal and field detecting circuit for video signal | |
JPS56119576A (en) | Pulse generating circuit | |
HK59096A (en) | Circuit arrangement for generating a clock signal | |
JPS5571358A (en) | Synchronizing separator circuit | |
JPS6424575A (en) | Circuit for providing special effect on video signal | |
JPS6413820A (en) | Decoder for manchester code | |
JPS57170673A (en) | Ultrasonic transmitting device | |
KR910003624Y1 (en) | Control signal mixing circuit of vertical blanking interval | |
JPS5491135A (en) | Vertical periodic signal sampling pulse generator circuit | |
DE69124845D1 (en) | Television device with processing of teletext signals | |
JPH01264368A (en) | Vertical synchronizing signal detecting circuit | |
JPS57142081A (en) | Signal discriminating circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |