JPS6413820A - Decoder for manchester code - Google Patents

Abstract

PURPOSE:To obtain a bit clock with high accuracy and less phase jitter and noise by providing a means generating a signal having a frequency being twice that of a Manchester code and recovering the bit clock based thereupon while using a PLL circuit. CONSTITUTION:A Manchester code is sent to an input terminal 11 and a signal S1 subject to band limit is supplied. The signal S1 is fed to a square circuit 12 and a signal S2 is outputted. The signal S2 is fed to a PLL circuit 14 via a BPF 13 and a signal S3 synchronized with the signal S2 is outputted. The signal S3 is subjected to 1/2 frequency division by a frequency divider circuit 15, a bit clock S4 is recovered and led to an output terminal 17 via an inverter 16. The bit clock S4 is fed also to a multiplier circuit 18, where it is multiplied with the signal S1. The output of the multiplier circuit 18 is fed to the LPF 19, from which a signal S5 represented by the Manchester code is outputted. The signal S5 is fed to a D-FF 21 and sampled by the bit clock S4 from the inverter 16 to obtain the clock synchronizing signal, which is led to an output terminal 22.