JPS6439760A - Complementary mos integrated circuit device - Google Patents

Abstract

PURPOSE:To contrive improvement in the degree of integration as well as to prevent the deterioration in characteristics by a method wherein, in the integrated circuit device constituting a plurality of parts of complementary circuits consisting of P- channel and N-channel MOS transistors, a circuit equal to an isolation region is constituted without providing the isolation region. CONSTITUTION:The active region 1c of a P-channel and the active region 1d of an N-channel only are formed integrally opposing each other, and an isolation region is not provided. A gate electrode 6b is connected by the first layer of Al wiring 8f, to which negative power source GND will be given, and at the same time, the gate electrode 6b is connected to the opposing gate electrode 6a with the first layer of Al wiring 8g. A negative source power is applied to the gate electrode 6a, and on the other hand, an N-channel transistor is brought into a cut-off state, and between each N-channel transistor of gate electrodes 5b and 7b is cut off. Also, positive source power is applied to a gate electrode 7a in the same manner as above, and on the other hand, a P-channel transistor is brought into a cut-off state. As a result, the number of Al wirings can be reduced, a high degree of integration can also be obtained, each transistor is brought into a cut-off state, and the generation of deterioration in characteristics can be prevented.