JPS6439662A - Data standardizer circuit - Google Patents

Abstract

PURPOSE:To prevent the fluctuation of a delay time from being increased, by switching the polarity of a read clock, and selecting plural delay time output of a read pulse signal, and supplying them to a synchronization circuit. CONSTITUTION:The read pulse signals S1-S5 read out from a recording medium are delayed sequentially by a delaying device 1, and inputted to a selector 2. The signal S3 is inputted to a phase detection circuit 3, and the circuit 3 outputs a signal S6 synchronizing with the average timing of each signal. The signal S6 inverts the polarity only in the active state of a signal S11 at a polarity switcher 4, and inputs an input signal S7 to the synchronizing circuit 5. Also, to the circuit 5, a single signal S8 selected by a selection code S10 is inputted. At the circuit 5, the signal S7 monitors the leading edge of the signal S8, and in detecting the leading edge, sends the signals S9 and S7 to the next circuit. By performing the above operation, it is possible to give a prescribed range of shift of a pitch to the center timing of a read data discrimination window.